An Integrated Approach To Power Domain And CDC Verification

Reducing power consumption is essential for both mobile and data center applications. Yet it is a challenge to lower power while minimally impacting performance. The solution has been to partition designs into multiple power domains which allow selectively reducing voltage levels or powering off partitions.

Traditional low power verification validates only the functional correctness of power control logic, it does not validate the impact of power logic on multi-clock logic.

The resolution of these clock domain crossing (CDC) issues requires new power-aware CDC analysis techniques:

• Low power-based clock and reset analysis
• Identification of low-power CDC paths and synchronization structures
• Identification and debug of low-power CDC violations

These low power design and verification methodologies and techniques are supported by refinement features in the IEEE 1801 Unified Power Format (UPF) and by the advanced capabilities of the Questa CDC and Questa Power-Aware verification tools, both from Siemens EDA, a part of Siemens Digital Industries Software. The latest UPF standards allow designers to begin the design and verification of power distribution networks earlier in the design flow and continue to refine the power networks throughout the design cycle. It is critical that designers start the CDC verification for the power distribution networks at the RTL level.

This low power CDC verification flow is an incremental change to the traditional RTL CDC verification flow. In the traditional flow, the low power elements are added to the design during the implementation phase of the project, so the low power CDC analysis will happen late in the design project. For Power Aware CDC verification, the power annotation adds the low power elements specified in the UPF to the RTL design.

Fig. 1: Power aware CDC verification flow.

The low power CDC analysis flow generally follows these five steps:

1. Generate parameterized UPF
2. Compile the RTL design
3. Run CDC analysis with UPF
4. Generate a power aware CDC report

Applying the methodology

For traditional designs, static structural analysis is used to identify both correct and incorrect CDC synchronization structures. For low power designs, both isolation and retention cells must be reviewed to ensure that incorrect CDC paths are correct as these cells should not disrupt correct CDC structures and should not introduce new CDC paths.

Advanced low power designs are taking advantage of common CDC verification techniques to ensure that data transfer between power domains are not corrupted by metastability. These CDC verification techniques include the identification of low power CDC paths and synchronization structures as well as support for both isolation and retention cells. Static structural analysis is a typical technique used to verify CDC paths, but for low power designs, both isolation and retention cells must be reviewed to ensure that incorrect CDC paths are identified and corrected.

With the power aware CDC analysis, designers are able to identify CDC paths affected by low power structures. Designers must ensure that isolation signals are correctly synchronized on CDC paths. Figure 2 shows both data and isolation enable sources in the same clock domain as the destination register.

Fig. 2: Isolation enable on correct clock domain.

In addition, CDC analysis should detect scenarios where isolation signals are not properly synchronized. In figure 3, there is no CDC crossing on the B1-B2 path that is represented in the RTL, but the B3-B2 CDC crossing is introduced with the UPF. When the isolation enable is in the clk2 domain is asserted or de-asserted, this may generate an asynchronous event that would cause metastability on the B2 register in the clk1 domain. Designers can also utilize the power aware CDC verification to validate correct retention cell usage.

Fig. 3: Isolation enable on incorrect clock domain.

Power aware CDC analysis detects cases where low power logic introduces combinational logic in the fan-in of a synchronizer. In figure 4, a 2DFF synchronizer structure is correctly implemented in RTL from B1 to the B2 synchronizer, but the isolation cell is described by the UPF and the isolation logic creates a combinational logic violation. Combinational logic fanin into synchronization structures will reduce the reliability of the synchronizer. Similar to CDC combinational logic violations, designers should ensure that design logic must first be registered before driving a CDC synchronizer.

Fig. 4: Isolation logic introduces combinational logic violation.

For reporting CDC results, the CDC paths related to low power logic are reported under separate schemes, as illustrated in these power aware CDC scheme examples.

pa_combo_logic

UPF adds combinational logic to a crossing.

pa_iso_en_no_sync

UPF isolation cell enable signal does not have a proper synchronizer.

pa_retention_restore

UPF retention register restore port does not have a proper synchronizer.

Conclusion

The low power specific schemes allow engineers to distinguish between non-power related CDC paths and CDC paths affected by low power logic. For teams focused on low power-related issues, the separate schemes allow them to easily identify, review, and debug low power CDC issues.

The successive refinement features in IEEE 1801 allow designers to begin the design and verification of power distribution networks earlier in the design flow and continue to refine the power networks throughout the design cycle. It is critical that designers start the CDC verification for the power distribution networks at the RTL level. Power aware CDC analysis enables design teams to start CDC analysis before the low power logic is added to the design during implementation and avoids detection of CDC errors late in the design flow at the gate-level.

Power management continues to be a critical need for IoT and mobile designs. With the advances in low power design, the low power design and verification methodologies and techniques continue to evolve. For a deeper treatment on the effects of advanced low power design on CDC design and verification, specifically the CDC issues caused by the addition of power control logic including isolation cells, retention cells, and level shifters, you can read the new Siemens EDA whitepaper Did Power Management Break My CDC Logic? The paper also describes the use of this flow on an actual design and shares results.