Are You Paying Proper Attention To Your ESD Design Windows?

Electrostatic discharge (ESD) issues in integrated circuit (IC) chip designs have become more critical at advanced semiconductor process nodes, due to shrinking transistor dimensions and oxide layer thickness [1]. There are many ESD design rules and flows that designers check for common ESD issues, such as topological checks for the existence of ESD protection devices, current density (CD) checks on the robustness of ESD discharge paths, and point-to-point (P2P) resistance checks to ensure the resistances from chip-level bumps to ESD protection devices are below certain design thresholds [2-3]. However, most ESD design rules available to IC chip designers don’t seem to take into account the fact that an ESD protection device must operate within the boundary of its ESD design window. Likewise, many designers don’t understand the impact a poorly-designed ESD design window can have on their designs.

ESD design windows

An ESD design window defines the voltage and current limits within which an ESD protection device operates during an ESD event. Figure 1 illustrates a typical ESD design window:

• V_DD is the normal operating voltage of the circuitry
• V_t2 and I_t2 are the voltage and electrical current, respectively, at which the ESD protection device will fail or break down to protect the victim circuitry.

Fig. 1: ESD design window.

On the right side of the ESD design window, as the voltage increases and reaches the region of circuitry breakdown voltage, the victim circuitry will be damaged. An ESD design window defines the voltage and electrical current operating region for the ESD protection device. Ideally, an ESD protection device is triggered or turned on at a voltage that is somewhere above the normal circuitry operating voltage, but will fail or break down when it reaches a voltage that is somewhere below the breakdown voltage of the victim circuitry.

If an ESD protection device is not properly designed such that it is not triggered or turned on before the victim circuitry reaches its breakdown voltage, the victim circuitry will break down before the ESD protection device has a chance to actually provide protection. Understanding the ESD design window of your ESD protection device is crucial to ensure that its upper voltage boundary does not reach or exceed the breakdown voltage of the victim circuitry.

At advanced semiconductor process nodes, circuitry operating voltages have decreased, as has the breakdown voltage of gate oxide for the process node. However, the breakdown voltage of gate oxide has decreased faster than the circuitry operating voltage, resulting in a smaller voltage range for ESD design windows at smaller process nodes [4-5]. This dichotomy makes it critical and challenging to carefully plan the operating voltage and electrical current of the ESD protection device to ensure that ESD protection devices operate inside their ESD design windows.

Estimating breakdown voltage

The circuitry operating voltage (V_DD in figure 1) is usually known to designers. After they select the type and size of an ESD protection device, they also know the operating and failing voltages and electrical current limits (such as V_t2 and I_t2 in figure 1) of the ESD protection device. The missing part is the determination of the upper voltage boundary of the ESD design window, which is limited by the breakdown voltage of the victim circuitry. This voltage is not an exact calculation—designers derive an estimated voltage based on the breakdown voltage of the victim circuitry. However, if the victim device (the device directly connected to the ESD protection device) is not directly connected to the ground (i.e., if there are several other devices connected in series between the victim device and the ground), using the breakdown voltage of the victim device alone as the breakdown voltage of the victim circuitry may be overly pessimistic, and the ESD protection device will fail or break down too soon. On the other hand, designers don’t want to over-estimate the breakdown voltage of the victim circuitry, such that the operating and failing voltages and electrical current limits of the ESD protection device extend into the region of the victim circuitry breakdown voltage, as this will result in the victim circuitry being damaged before the ESD protection device fails or breaks down.

To properly define the upper voltage boundary of an ESD design window, some IC chip designers use the following method to determine the breakdown voltage of the victim circuitry, as shown in figure 2:

• First examine all possible electrical paths between the victim device and the ground,
• Add up the breakdown voltages of all device junctions on each path,
• Find the path with the lowest total breakdown voltage, and
• Use this lowest total breakdown voltage as the breakdown voltage of the victim circuitry.

Fig. 2: Manual identification and calculation of the lowest total breakdown voltage examines all possible electrical paths between a victim device and the ground.

The need to properly determine the upper voltage boundary of an ESD design window exists in every scenario where an ESD protection device is used. Depending on where in the circuitry an ESD protection device is placed, an IC designer may need to find out the lowest total breakdown voltage for electrical paths between:

• A signal bump and a power or ground bump,
• A power bump and a ground bump, and
• A victim device and a power or ground bump, etc.

In a complex IC chip design, it is virtually impossible to manually examine all possible electrical paths, add up the breakdown voltages of all device junctions on each path, and identify the path with the lowest total breakdown voltage. Fortunately, there are electronic design automation tools that can help design teams accurately identify the lowest total breakdown voltage for any electrical path, no matter how complex. With this knowledge, designers can estimate the most appropriate upper voltage boundary for the ESD design window.

We’ll look at how the process works using the Calibre PERC reliability verification platform from Siemens EDA.

Automated breakdown voltage calculation

The Calibre PERC reliability verification platform allows designers to write rule-based flows for checking complex ESD problems in IC chip designs at the intellectual property (IP), block, and full-chip levels. We begin by writing a Calibre PERC flow that will analyze a netlist and output the path with the lowest total breakdown voltage between two given pins.

The Calibre PERC flow accepts either a layout database (GDSII or OASIS) or a schematic netlist (SPICE) as input. If using a layout as input, the Calibre PERC platform first runs a layout vs. schematic (LVS) extraction to generate an electrically-equivalent layout netlist from the layout database. Starting with the SPICE netlist or the generated layout netlist, the Calibre PERC platform traverses the entire hierarchy of the netlist to identify all possible electrical paths between two given pins. For each electrical path, the Calibre PERC platform identifies all device junctions on the path. Based on an input file containing a table of device names and breakdown voltages of device junctions, the Calibre PERC platform calculates the total breakdown voltage of all device junctions on each path. Finally, the flow outputs the path (including all devices on the path) with the lowest total breakdown voltage, as well as the value of the lowest total breakdown voltage. Figure 3 illustrates this flow starting with the layout database.

Fig. 3: The Calibre PERC flow calculates the lowest total breakdown voltage between two given pins.

Designers can then review the output results of this flow in the Calibre RVE results viewer, and the Calibre DESIGNrev layout viewer to see a visual representation of the electrical path with the lowest total breakdown voltage in a schematic or layout view. Figure 4a shows the results of the electrical path with the lowest total breakdown voltage, with all device names on the path, while 4b is the schematic view of the two given pins and all devices on the electrical path with the lowest total breakdown voltage. This path with the lowest total breakdown voltage is also the weakest path between the two given pins.

Fig. 4: (a) Calibre RVE results showing the devices on the electrical path between two given pins FG and V_SS, which is the path (from FG to VSS) with the lowest total breakdown voltage, (b) Calibre RVE schematic view of the two pins and the devices on the path.

Knowing the lowest total breakdown voltage can help IC chip designers more accurately estimate the upper voltage boundary of ESD design window, ensuring that ESD protection device operation is optimized while providing full protection to the victim circuitry.

Summary

Meeting ESD design protection requirements is a critical part of today’s IC chip designs. Automated EDA flows that check for some common ESD issues, such as the connectivity to ESD devices or the robustness of ESD discharge paths, are readily available to IC chip designers, either through foundry-supported PDKs or custom rule decks. However, designers are often unaware of automated EDA flows that can help IC chip designers calculate the breakdown voltage of victim circuitry, which can help them more precisely define the upper voltage limit of an ESD design window. Using a tool like the Calibre PERC platform allows designers to quickly and accurately identify the electrical path between two given pins with the lowest total breakdown voltage. This lowest total breakdown voltage can be used to more accurately estimate the upper voltage limit of an ESD design window, ensuring adequate ESD protection for design circuitry.

For more information, read the technical paper A better way to estimate breakdown voltage for ESD design windows on Siemens EDA.

References

1. A. Ille et al., “Reliability aspects of gate oxide under ESD pulse stress,” 2007 29th Electrical Overstress/Electrostatic Discharge Symposium (EOS/ESD), 2007, pp. 6A.1-1-6A.1-10, doi: 10.1109/EOSESD.2007.4401771
2. EDA Tool Working Group (ESD Association), “ESD Association Technical Report for ESD Electronic Design Automation Checks”, ESD TR18.0-01-14. https://www.esda.org/store/standards/product/4/esd-tr18-0-01-14
3. D. Yan, “Ensuring Robust ESD Protection in IC Designs,” Siemens Digital Industries Software, 2017. https://resources.sw.siemens.com/en-US/white-paper-ensuring-robust-esd-protection-in-ic-designs
4. O. Semenov, H. Sarbishaei, and M. Sachdev, “ESD Protection Device and Circuit Design for Advanced CMOS Technologies,” Springer Science, 2010. P. 14. https://link.springer.com/book/10.1007/978-1-4020-8301-3
5. A. Dong, J. Xiong, S. Mitra, W. Liang, R. Gauthier Jr., and A. Loiseau, “Comprehensive Study of ESD Design Window Scaling Down to 7nm Technology Node”, 2018 40th Electrical Overstress/Electrostatic Discharge Symposium (EOS/ESD), 23-28 September 2018. https://ieeexplore.ieee.org/document/8509689.