Author's Latest Posts

Developing Smarter, Safer Cars with ADAS IP
By Cadence - 16 Jan, 2019 - Comments: 0

By Charles Qi, Sr. Design Engineering Architect, and Neil Robinson, Product Marketing Director, IP Group, Cadence Today’s cars are a full-fledged electronic system on wheels, where every part is interrelated and must be designed, optimized, and verified simultaneously. As a result, it’s important to apply a holistic approach when developing automotive systems, taking into consideration t... » read more

Consolidating RF Flow for High-Frequency Product Design
By Cadence - 09 Jan, 2019 - Comments: 0

Design flows are currently fragmented due to the use of poorly connected EDA tools for various design tasks. Fragmented flows are unable to meet new challenges such as increased system and circuit complexity, stricter bandwidth requirements, smaller device sizes, and changing packaging needs. In this white paper, we look at how the Cadence Virtuoso RF Solution provides a single, well-integrated... » read more

Enabling Embedded Vision Neural Network DSPs
By Cadence - 19 Dec, 2018 - Comments: 0

Neural networks are now being developed in a variety of technology segments in the embedded market, from mobile to surveillance to the automotive segment. The computational and power requirements to process this data is increasing, with new methods to approach deep learning challenges emerging every day. Vision processing systems must be designed holistically, for all platforms, with hardwa... » read more

Reducing Latency, Power, and Gate Count with Floating-Point FMA
By Cadence - 12 Dec, 2018 - Comments: 0

Today’s digital signal processing applications such as radar, echo cancellation, and image processing are demanding more dynamic range and computation accuracy. Floating-point arithmetic units offer better precision, higher dynamic range, and shorter development cycles when compared with fixed-point arithmetic units. Minimizing the design’s time to market is more important than ever. Algori... » read more

Delivering Superior Throughput For EDA Verification Workloads
By Cadence - 28 Nov, 2018 - Comments: 0

Perhaps no industry is more competitive than modern electronics manufacturing and chip design. As consumers, we take it for granted that electronic devices continue to get faster, cheaper, and more capable with each generation. From smart watches to industrial controls to electronic heart-rate monitors, electronics manufacturers are challenged to build smarter, more complex devices leveraging s... » read more

Delivering Superior Throughput for EDA Verification Workloads
By Cadence - 07 Nov, 2018 - Comments: 0

Perhaps no industry is more competitive than modern electronics manufacturing and chip design. As consumers, we take it for granted that electronic devices continue to get faster, cheaper, and more capable with each generation. From smart watches to industrial controls to electronic heart-rate monitors, electronics manufacturers are challenged to build smarter, more complex devices leveraging s... » read more

A Method to Measure Die Pad Capacitance
By Cadence - 24 Oct, 2018 - Comments: 0

This paper defines a method to measure the chip die pad capacitance using time delay reflectometry (TDR). This method is useful for measuring the low-value capacitance that is present at the end of a transmission line. In all protocol specifications, pad capacitance is an important electrical parameter to be measured because it directly affects the bandwidth. However, it is a challenge to me... » read more

Analog Reliability Analysis for Mission-Critical Applications
By Cadence - 26 Sep, 2018 - Comments: 0

Rapidly increasing electrical content in automobiles is driving the need for revolution in analog integrated circuit (IC) design methodology. Compared to designing for consumer electronics, designing for mission-critical applications—industrial, medical, space, and automotive—requires a different approach to reliability analysis. We will explore how reliability analysis needs to change for ... » read more

Accelerating SoC Time To Market With Cloud-Based Verification
By Cadence - 12 Sep, 2018 - Comments: 0

This paper discusses the growing use of cloud and hybrid cloud environments among semiconductor design and verification teams. The schedule and efficiency benefits seen by verification teams using cloud are specifically highlighted, due to the considerable compute requirements associated with verification of advanced node SoCs, and the significant impact verification has on the overall SoC proj... » read more

Cadence Cloud—The Future Of Electronic Design Automation
By Cadence - 16 Jul, 2018 - Comments: 0

Design complexity and competitive pressures are driving electronics developers to seek innovative solutions to gain competitive advantage. A key area of investigation is applying the power of the cloud to electronic design automation (EDA) to dramatically boost productivity. Grounded in its long history of providing hosted design solutions (HDS) and internal experience with cloud-based design, ... » read more

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