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Compressing Datasets Created During Silicon Design

A method for compressing data during silicon semiconductor design.

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Authors: Guru Rao, Distinguished Engineer; Shakir Abbas, Software Engineering Group Director; Mohammad Mirfendereski, Configuration Management Architect; Cadence. Harsh Sharangpani, CEO and CTO; Rajesh Patil, VP-Business Development; Ascava.

During the design cycle for modern semiconductor components, a very large amount of data is generated and stored, often accumulating to hundreds of terabytes. Traditional compressor solutions are inadequate, and data footprints remain unwieldy and expensive to manage. To address this issue, Cadence evaluated a compressor called the Ascava App. This app addressed the problem of reducing large data footprints and can be incorporated into the infrastructure flows of enterprises to significantly cut data storage and communication costs and to improve transfer speeds on datasets created during the silicon design process.

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