Author's Latest Posts

Process Model Calibration: Building Predictive and Accurate 3D Process Models
By Coventor - 20 Aug, 2020 - Comments: 0

The semiconductor industry has always faced challenges caused by device scaling, architecture evolution and process complexity and integration. These challenges are coupled with a need to provide new technology to the market quickly. In the initial stages of semiconductor technology development, innovative process flow schemes must be tested using silicon test wafers. These wafer tests are leng... » read more

Speeding Up Process Optimization With Virtual Processing
By Coventor - 16 Jul, 2020 - Comments: 0

Advanced CMOS scaling and new memory technologies have introduced increasingly complex structures into the device manufacturing process. For example, the increase in NAND memory layers has achieved greater vertical NAND scaling and higher memory density, but has led to challenges in high aspect ratio etch patterning and foot print scaling issues. Unique integration and patterning schemes have b... » read more

A Benchmark Study Of Complementary-Field Effect Transistor (CFET) Process Integration Options: Comparing Bulk vs. SOI vs. DSOI Starting Substrates
By Coventor - 17 Jun, 2020 - Comments: 0

Sub-5 nm logic nodes will require an extremely high level of innovation to overcome the inherent real-estate limitations at this increased device density. One approach to increasing device density is to look at the vertical device dimension (z-direction), and stack devices on top of each other instead of conventionally side-by-side. The fabrication of a Complementary-Field Effect Transistor (CF... » read more

A Benchmark Study Of Complementary-Field Effect Transistor (CFET) Process Integration Options Done By Virtual Fabrication
By Coventor - 01 Jun, 2020 - Comments: 0

Four process flow options for Complementary-Field Effect Transistors (C-FET), using different designs and starting substrates (Si bulk, Silicon-On-Insulator, or Double-SOI), were compared to assess the probability of process variation failures. The study was performed using virtual fabrication techniques without requiring fabrication of any actual test wafers. In the study, Nanosheet-on-Nanoshe... » read more

Defect Evolution In Next Generation, Extreme Ultraviolet Lithography
By Coventor - 18 Mar, 2020 - Comments: 1

Extreme ultraviolet (EUV) lithography is a promising next generation lithography technology that may succeed optical lithography at future technology nodes. EUV mask infrastructure and manufacturing of defect-free EUV mask blanks is a key near term challenge in the use of EUV lithography. Virtual fabrication is a computerized technique to perform predictive, three dimensional modeling of sem... » read more

Speeding Up Process Optimization Using Virtual Fabrication
By Coventor - 22 Jan, 2020 - Comments: 0

Author: Joseph Ervin Director, Semiconductor Process and Integration Lam Research Advanced CMOS scaling and new memory technologies have introduced increasingly complex structures into the device manufacturing process. For example, the increase in NAND memory layers has achieved greater vertical NAND scaling and higher memory density, but has led to challenges in high aspect ratio etch patte... » read more

N7 FinFET Self-Aligned Quadruple Patterning Modeling
By Coventor - 16 Dec, 2019 - Comments: 0

In this paper, we model fin pitch walk based on a process flow simulation using the Coventor SEMulator3D virtual platform. A taper angle of the fin core is introduced into the model to provide good agreement with silicon data. The impact on various Self-Aligned Quadruple Patterning process steps is assessed. Etch sensitivity to pattern density is reproduced in the model and provides insight on ... » read more

A Benchmark Study Of Complementary-Field Effect Transistor (CFET) Process Integration Options
By Coventor - 21 Nov, 2019 - Comments: 0

Sub-5 nm logic nodes will require an extremely high level of innovation to overcome the inherent real-estate limitations at this increased device density. One approach to increasing device density is to look at the vertical device dimension (z-direction), and stack devices on top of each other instead of conventionally side-by-side. [1] The fabrication of a Complementary-Field Effect Transistor... » read more

Advances In 3D CMOS Image Sensors Optical Modeling: Combining Realistic Morphologies With FDTD
By Coventor - 16 Oct, 2019 - Comments: 0

This paper describes an innovative methodology to investigate the relationship between device morphology and the optical performance of CMOS image sensors. By coupling a FDTD-based 3D Maxwell solver with silicon-accurate process modeling software, we have been able to analyze the sensitivity of image sensor quantum efficiency with respect to statistical variations in nm-scale device topology. A... » read more

Influence Of SiGe On Parasitic Parameters in PMOS
By Coventor - 27 Sep, 2019 - Comments: 0

In this paper, simulation-based design-technology co-optimization (DTCO) is carried out using the Coventor SEMulator3D virtual fabrication platform with its integrated electrical analysis capabilities [1]. In our study, process modeling is used to predict the sensitivity of FinFET device performance to changes in a silicon germanium epitaxial process. The simulated process is a gate-last flow p... » read more

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