A look at four process flows using different designs and starting substrates to assess design failures.
Four process flow options for Complementary-Field Effect Transistors (C-FET), using different designs and starting substrates (Si bulk, Silicon-On-Insulator, or Double-SOI), were compared to assess the probability of process variation failures. The study was performed using virtual fabrication techniques without requiring fabrication of any actual test wafers. In the study, Nanosheet-on-Nanosheet stacked channels provided superior process integration robustness compared to Nanowire-On-Fin stacked channels. For the Nanowire-On-Fin option, using an SOI substrate as the starting material (compared to Si bulk or DSOI) also strongly reduced process variation failure rates.
To read more, click here.
 |
 |
 |
 |
 |
 |
 |
 |
 |
 |
Leave a Reply