Comparative Analysis of CFET and NSFET Architectures (TU Munich, IIT)


A new technical paper titled "Impact of Aging, Self-Heating, and Parasitics Effects on NSFET and CFET" was published by researchers at TU Munich and Indian Institute of Technology. Abstract "This work presents a comparative analysis of complementary field-effect transistor (CFET) and nanosheet FET (NSFET) architectures, with a focus on self-heating effects (SHEs), negative bias temperature ... » read more

Material Properties of Si/SiGe Multi-layer Stacks For CFETs (Imec, Ghent U, et al.)


A new technical paper titled "Epitaxial Si/SiGe Multi-Stacks: From Stacked Nano-Sheet to Fork-Sheet and CFET Devices" was published by researchers at Imec and Ghent University, et al. Abstract "After a short description of the evolution of metal-oxide-semiconductor device architectures and the corresponding requirements on epitaxial growth processes, the manuscript describes the material pr... » read more

CFETs with Optimized Buried Power Rails


A technical paper titled "Buried power rail to suppress substrate leakage in complementary field effect transistor (CFET)" was published by researchers at Korea University and Sungkyunkwan University. Abstract "In the pursuit of minimizing the track height in standard cell, a design innovation incorporating complementary field-effect transistors (CFETs) and Buried Power Rail (BPR) technolog... » read more

A Benchmark Study Of Complementary-Field Effect Transistor (CFET) Process Integration Options Done By Virtual Fabrication


Four process flow options for Complementary-Field Effect Transistors (C-FET), using different designs and starting substrates (Si bulk, Silicon-On-Insulator, or Double-SOI), were compared to assess the probability of process variation failures. The study was performed using virtual fabrication techniques without requiring fabrication of any actual test wafers. In the study, Nanosheet-on-Nanoshe... » read more