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Jesse Allen

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Jesse Allen is the Knowledge Center administrator and a senior editor at Semiconductor Engineering.

Author's Latest Posts

Week In Review: Design, Low Power
By Jesse Allen - 09 Sep, 2022 - Comments: 0

Revenue for the top 10 IC design houses globally hit US$ 39.6 billion in 2Q22, a 32% growth over the prior year, according to a Trendforce report. The firm contends this growth trend will be difficult to maintain due to the high preceding base period and overall worse market conditions. Renesas introduced a RISC-V MCU specifically optimized for advanced motor control systems. The new ASSP in... » read more

Startup Funding: August 2022 Sortable Funding Chart
By Jesse Allen - 08 Sep, 2022 - Comments: 0

Below is a sortable chart that accompanies your e-book purchase of Semiconductor Engineering's August 2022. Startup Funding report.  Simply click on the top headers to determine your primary sort. [table id=52 /] The complete ebook (over 40 pages) can be found here. » read more

Startup Funding: August 2022
By Jesse Allen - 07 Sep, 2022 - Comments: 0

Investors funneled $1.9 billion into startups last month. The total was down from the previous few months for companies tracked by Semiconductor Engineering, but still a strong showing for the chip industry and related technologies. By market segment, power devices were a bright spot in August's funding, with 12 companies receiving new financing rounds. A manufacturer of multilayer ceramic c... » read more

Blog Review: Sept. 7
By Jesse Allen - 07 Sep, 2022 - Comments: 0

Cadence's Paul McLellan shares highlights from the recent Hot Chips tutorial on CXL and how enhanced memory pooling enables new memory usage models as CXL 3.0 approaches the same speed as DRAM. Synopsys' Sam Tennent and Kamal Desai highlight the emergence of virtual prototyping, its synergy with continuous integration and development setups, and the benefits when these disciplines are combin... » read more

Blog Review: Aug. 31
By Jesse Allen - 31 Aug, 2022 - Comments: 0

Cadence's Paul McLellan wonders what's happened to 450mm wafers as equipment development efforts end, the only wafer fab is decommissioned, and manufacturers see little likelihood to recoup further investment in R&D. Synopsys' Manuel Mota finds that the scale and modular flexibility of chiplets can help meet narrowing time-to-market windows and looks at how UCIe provides a complete stack... » read more

Research Bits: Aug. 30
By Jesse Allen - 30 Aug, 2022 - Comments: 0

Through glass vias Researchers from the Chinese Academy of Sciences (CAS) developed a Through Glass Via (TGV) process for 3D advanced packaging, which they say enables low transmission loss and high vacuum wafer-level packaging of high-frequency chips and MEMS sensors. TGV is a vertical interconnection technology applied in wafer-level vacuum packaging. The researchers found that it has goo... » read more

Blog Review: Aug. 24
By Jesse Allen - 24 Aug, 2022 - Comments: 0

Synopsys' Manuel Mota presents an overview of some of the newest multi-chip module packaging types and their advantages and disadvantages for different kinds of applications, as well as the importance of die-to-die interfaces. Cadence's Steve Brown finds that innovative products require that electronics be analyzed in the context of the environment in which they run, making mechanical and el... » read more

Research Bits: Aug. 23
By Jesse Allen - 23 Aug, 2022 - Comments: 0

Algae-powered microprocessor Engineers from the University of Cambridge, Arm Research, Scottish Association for Marine Science, and Norwegian University of Science and Technology used a widespread species of blue-green algae to power an Arm Cortex M0+ microprocessor continuously for over a year. The algae, Synechocystis, is non-toxic and harvests energy from photosynthesis. The tiny electri... » read more

Week In Review: Design, Low Power
By Jesse Allen - 19 Aug, 2022 - Comments: 0

The U.S. Commerce Department's Bureau of Industry and Security (BIS) issued new export controls on EDA software aimed at designing gate-all-around FETs, which manufacturers plan to implement starting at 3nm (Samsung) and 2nm (Intel and TSMC). Specifically, the ruling controls export of software that is specially designed for implementing RTL to GDSII (or an equivalent standard) for GAA FET desi... » read more

Blog Review: Aug. 17
By Jesse Allen - 17 Aug, 2022 - Comments: 0

Synopsys' Steve Pateras explains the basics of silicon lifecycle management and how it can help monitor, analyze, and optimize both semiconductor and end-user systems throughout the product value chain, from design and manufacturing to testing and maintenance. Siemens' Heather George considers the current state of 3D chiplet-based designs and efforts to standardize chiplet models and deliver... » read more

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