Blog Review: Sept. 28

Automotive digital twins; class members in SystemVerilog; AI memory bottlenecks; MEMS gyroscopes.


Cadence’s Paul McLellan shares more highlights from the recent Hot Chips, including some very large chips and accelerators for AI and deep learning, new networks and switches, and mobile and edge processors.

Synopsys’ Marc Serughetti considers the different use cases for digital twins in automotive and how they can help determine the impact of software on verification, test, and validation activities as well as enable early hardware and software integration and frontload testing.

Siemens’ Chris Spear discusses class member visibility in SystemVerilog along with what to do when you want to limit access to members.

Rambus’ Steven Woo discusses the AI memory bottleneck and other key takeaways from the AI Hardware Summit, such as the challenge of developing hardware and software that addresses a wide range of workloads.

Arm’s Paul Williamson argues that real-time 3D content will be the next big disruptor in consumer tech, expanding from entertainment and gaming to areas such as automotive, healthcare, industrial, construction, and navigation.

Ansys’ Laura Carter points to challenges for color blind drivers and how simulation can help create more user-friendly displays by predicting what color blind people will see in response to numerous factors, such as display brightness, resolution, contrast, and illuminance in ambient lighting conditions.

Coventor’s Arnaud Parent explores modeling a MEMS-based whole-angle gyroscope that could be used in advanced navigation applications, such as north finding or dead reckoning navigation.

SEMI’s Mark da Silva details five key technology stages essential to implementing an autonomous factory encompassing the entire semiconductor product life cycle, from front-end to back-end, and the path for semiconductor companies to implement smart manufacturing technologies.

Renesas’ Chiaki Seiji considers the challenges in porting applications across Arm and RISC-V CPUs, including tight coupling of hardware and applications, varying peripherals, and the possibility of incompatible general-purposes programs such as middleware.

Intel’s Jakob Engblom examines the Device Modeling Language (DML) that can be used to model devices such as a timer, serial port, interrupt controller, accelerator block, or Ethernet interface and argues for the productivity benefits of a domain-specific language.

Western Digital’s Thomas Ebrahimi considers how large 3D printing systems could enable microfactories that offer a proximal, just-in-time option for manufacturing and counter global supply chain challenges.

And don’t miss the blogs featured in the latest Systems & Design newsletter:

Technology Editor Brian Bailey explains why, at a time when many pieces of an EDA flow are being fused together, pressure is mounting to make it a lot more open and amenable to external extension and enhancement.

Siemens’ WeiLii Tan advises catching IP correctness problems early in the design flow.

Synopsys’ Mike Gianfagna looks at how data centers have undergone a fundamental shift, both in the volume of data and how it is processed.

Renesas’ Andrew Cowell examines a single architecture to manage the power demands of the many different types of processors in a data center.

Codasip’s Mike Eftimakis explores different configurations and combinations of IP in a single environment.

Cadence’s Ben Gu argues that electromagnetic analysis is essential for interposer designs.

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