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Week In Review: Design, Low Power

Big data comes to EDA; memory modeling; Arm’s cloud roadmap; open-source test and measurement chips; 8-bit floating point for AI; quantum grants.

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Cadence unveiled a big data analytics infrastructure to unify massive data sets across all Cadence computational software. The Joint Enterprise Data and AI (JedAI) Platform aims to optimize multiple runs of multiple engines across an entire SoC design and verification flow. It combines data from its AI-driven Cerebrus implementation and Optimality system optimization solutions, along with the newly announced Verisium for verification to enable management of both structured and unstructured data, including design data, workload data, and workflow data.

Verisium is a suite of verification applications leveraging big data and AI. Current apps include regression failure triage automation, source code revision comparison and management, multi-run waveform analysis, interactive and post-process debug, and verification management. The platform enables all verification data, including waveforms, coverage, reports, and log files, to be brought together in the Cadence JedAI Platform. MediaTek, Renesas, Samsung Electronics, and STMicroelectronics noted adoption of the JedAI or Verisium platform.

Keysight added new memory design capabilities to the latest version of its PathWave ADS 2023 for high-speed digital design. The new capabilities enable modeling and simulation of LPDDR4, LPDDR5, GDDR6, GDDR7, HBM2/2E, HBM3, and NAND. It predicts the closure and equalization of the data eye, enables pathfinding in pre-silicon digital twins to address current integration requirements such as forwarded clocking and timing, and constructs parameterized memory buses using a new pre-layout builder to explore system trade-offs.

Arm updated its Neoverse roadmap. The Neoverse V2 platform for cloud, hyperscale, and HPC workloads will include the company’s newest V-series core and the Arm CMN-700 mesh interconnect along with Armv9 architectural security enhancements. It also detailed the Neoverse E2 Platform, which combines the Cortex-A510 CPU with the scalable Neoverse CMN-700 and N2 system backplane. E2 targets cloud technology in constrained applications with a scalable range of core counts, SystemReady compatibility, and PCIe, CXL, IO and interfaces. Additionally, the company said that a new generation of its performance and efficiency focused N-Series will be available in 2023.

The National Institute of Standards and Technology (NIST) and Google will cooperate to produce a suite of chips with specialized structures for measuring and testing the performance of the components placed on top of it, including new kinds of memory devices, nanosensors, bioelectronics, and advanced devices needed for artificial intelligence and quantum computing. NIST anticipates designing as many as 40 different chips optimized for different applications. The chips will be manufactured by SkyWater Technology. Google will pay the initial cost of setting up production and will subsidize the first production run. NIST, with university research partners, will design the circuitry for the chips. The circuit designs will be open source, allowing academic and small business researchers to use the chips without restriction or licensing fees.

AI

Flex Logix introduced a hardware and software-ready mini-ITX x86 system designed to help customers customize, build, and deploy edge and embedded AI systems. The InferX Hawk system includes the Flex Logix InferX X1 AI accelerator chip, AMD Ryzen Embedded R2314 SoC, InferX Runtime software, and the EasyVision platform running Linux or Windows. It particularly targets a range of smart vision and video applications.

Arm, Intel, and Nvidia proposed a specification for an 8-bit floating point (FP8) format that could provide a common interchangeable format that works for both AI training and inference and allow AI models to operate and perform consistently across hardware platforms. A paper by the companies proposes two FP8 variants: E4M3 (4-bit exponent and 3-bit mantissa) and E5M2 (5-bit exponent and 2-bit mantissa). “FP8 minimizes deviations from existing IEEE 754 floating point formats with a good balance between hardware and software to leverage existing implementations, accelerate adoption, and improve developer productivity,” wrote Shar Narasimhan, a director of product marketing at Nvidia, in a blog. “Testing the proposed FP8 format shows comparable accuracy to 16-bit precisions across a wide array of use cases, architectures, and networks. Results on transformers, computer vision, and GAN networks all show that FP8 training accuracy is similar to 16-bit precisions while delivering significant speedups.” The three companies plan to submit the proposal to IEEE.

Automotive

Arteris IP and Arm are teaming up on automotive electronics, with the aim of offering integrated and optimized solutions that combine Arm processors and Arteris system IP. As part of the deal, Arm licensed a portfolio of released and future Arm Cortex CPUs to Arteris IP to expand and accelerate delivery of automotive solutions.

Keysight announced a new automotive serializer/deserializer (SerDes) receiver (Rx) compliance test solution to verify MIPI A-PHY devices for automotive applications. The Rx compliance test solution recreates a compliant transmitter that generates a controlled distorted signal (worst case) and analyzes the impact of the distortions on the receiver’s capability to correctly sample transmitted data. The solution was developed in collaboration with BitifEye Digital Test Solutions and Wilder Technologies, with the support of Valens Semiconductor.

Infineon introduced a smart high-side MOSFET gate driver for 12 V/ 24 V automotive application with integrated wire protection. This gate driver features two output channels for two different MOSFET structures, either back-to-back common source plus a pre-charging path or common drain. The enhanced driver capability to turn-on and turn-off allows it to scale up the amount of MOSFETs to manage larger load currents.

Teraki deployed its automotive radar detection software that identifies static and moving objects on Infineon’s ASIL-D compliant AURIX TC4x microcontrollers.

SiFive announced three products as part of a new roadmap for automotive applications, including infotainment, cockpit, connectivity, ADAS, and electrification.

Power devices

Infineon introduced new 800 V and 950 V AC-DC integrated power stages (IPS) as part of its fixed-frequency (FF) CoolSET portfolio, which combines a PWM controller IC with high voltage superjunction MOSFETs in a single package. The new devices enable both isolated and non-isolated topologies such as flyback or buck and operate at switching frequencies of 100 kHz as well as 65 kHz. Housed in a DIP-7 package, they target applications such as auxiliary power supplies for home appliances, AC-DC converters, battery chargers, solar energy systems, and motor control and drives.

Renesas Electronics used Andes Technology’s entry-level RISC-V core as the computing engine in the new G020 RISC-V MCU ASSP for motor control applications.

Quantum computing

A consortium led by Wave Photonics with partners Alter Technology TUV NORD UK, Senko Advanced Components, University of Southampton, and University of Bristol were awarded a £0.5 million (~$0.6M) grant from Innovate UK to develop packaging solutions for quantum photonic integrated circuits. The Quantum Photonic Integrated Circuit PACkaging (QPICPAC) project will develop a template-driven approach to minimize custom development requirements and costs for quantum technology companies. Quantum Dice, a startup developing QPIC-based quantum random number generators, will be acting as a trial customer for the project to provide insights into the needs of quantum photonics companies intending to make products in high volume.

Aegiq and Fraunhofer CAP were awarded a £0.5 million (~$0.6M) grant from Innovate UK to develop a field-deployable high-performance quantum light source integrated solution. Such a light source could be used for delivering high-speed quantum key distribution and quantum information processing, as well as being a brighter source for imaging or sensing applications.

The Innovation Institute at the Massachusetts Technology Collaborative (MassTech) will provide a $3.5 million grant for the Experiential Quantum Advancement Laboratories (EQUAL) at Northeastern University. The aim is to develop next-generation quantum technologies, boost training in quantum information science and engineering for students and workers, and establish greater partnerships among industry and government around quantum sensing and related technologies.

Amazon Web Services (AWS) will provide funding for research into quantum networking at Harvard University. It will focus specifically on research projects in the areas of quantum memory, integrated photonics, and quantum materials. It will also help upgrade quantum fabrication capabilities  at Harvard’s Center for Nanoscale Systems.

Read more

Find out why early solutions are needed thermal becomes a systems issue in the latest Low Power-High Performance newsletter. Also learn why fundamental rethinking will be needed to significantly reduce the power being consumed by machine learning and why new ways of collecting and analyzing data is having an impact on design and monitoring of chips.

Is there about to be a major disruption in the EDA industry? A view from academics features in the latest Systems & Design newsletter. Plus, the impact of climate change on data centers and whether the industry is responding fast enough to changing demands on verification.



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