Automation And Correct By Construction Will Empower 3D-IC Adoption

When research on 3D ICs was in full swing around 2009, I had been researching on how through-silicon-via (TSV) was related to thermal in a semiconductor chip-making company, and it seemed logical that 3D ICs would become mainstream. However, during the past 10 years, use of 3D stacked die has been applied to only a few applications, such as memory or image sensors, and the 2.5D solution using interposer has been mainly used for FPGAs, all with a lot of manual efforts. Furthermore, there has been no major innovation from the 2D system (where each die has its own package and all components are stacked on a system board) to 3D ICs.

In the meantime, I have been busy investigating the impact of power noise from the board to package and chip, which is gradually spreading to the area where signal noise and temperature are deteriorating system performance.

In recent years, AI, high-performance computing (HPC), and 5G have led to the need to rapidly analyze a vast amount of data, communication between various entities, and the data created by that communication, which is forcing a change to the topography of semiconductors.

This has led to the use of various SiPs (System-in-Package) where multiple dies and components are contained within a single package and facilitated the development of advanced packages for high bandwidth, high performance, and low cost, such as silicon interposer, Fan Out, and hybrid-like EMIB (Embedded Multi-Die Interconnect Bridge).

I am convinced that SiPs consisting of SoCs and stacked HBMs (High Bandwidth Memory), and advanced packaging will be a primary chip form factor for AI, HPC, and 5G devices focused on a co-analysis solution that encompasses the full SiP system at the early and sign-off design stages to reduce power, signal, and thermal noise.

However, even if I provide a solution that predicts and solves the noise in advance, unless the analysis result is directly reflected in the design, it is very difficult to find and fix the cause of the problem in a SiP because it is much more complex than a 2D system. Furthermore, the SiP is much more vulnerable to coupling noise because the distance between the chip and package is much closer.

Since the person designing the chip and the person designing advanced packaging are not the same, it is very difficult for two designers who have limited knowledge about each other to solve the problem, even if they find the weak part by electronic noises.  And if the chip and package are designed by different companies, as they are in many cases, expecting communication between the two is even less realistic.

Therefore, the best way to avoid the potential coupling noise is to have a layout tool with the ability to draw noise-resistant layouts during implementation.

The gap between noise analysis and real design brought me to Synopsys.

A 2.5D IC composed of an SoC, stacked HBMs, and silicon interposer is regarded as the popular structure for AI, HPC, and 5G devices. The quality of data computing depends on vertical (high-speed interface like SerDes and power/ground delivery network) and horizontal channels (memory channel) inside the silicon interposer. Minimized jogs and vias, no cross pattern, regular shape and pitch between the horizontal channels, and shortest path for the vertical channels connected from C4 bump to TSV and microbump and more shielding make the strong to electronic noise layouts.

However, the silicon interposer has been designed manually based on full-custom layout tools. The larger the number of channels due to new HBM generation, such as HBM2, HBM2E and HBM3, the longer the routing time and the lower the productivity.

Manual routing for a huge number of channels makes it harder to keep the shape and spacing of the channel constant, and electronic noise-resistant channel routing seems impossible, since a typical layout designer generally has a knowledge how to implement a design being strong against signal and power noise.

Synopsys’ IC Compiler II place-and-route solution includes highly automated silicon interposer routing that directly addresses all the inconveniences of conventional manual routing. The auto-routing supports the horizontal channel routing between the SoC and HBMs, as well as customized FPGA forms. For the vertical channel of high-speed interface IP and power/ground networks, IC Compiler II provides auto placement among microbumps of multi-die, TSV, and C4 bumps of interposer, as well as auto connection among the components.

Such auto placement and routing enables a user to shrink turnaround time (TAT at least a few days or weeks in the manual custom routing to a few hours or within one day. This automated feature is important to achieve quick silicon interposer design improvement after analysis.

Auto-routing on one or a few HBM channels takes just a few decades minute it allows the user to perform various feasibility checks with diverse channel options and finalize the optimal channel pattern.

Above all, the IC Compiler II interposer routing capability helps the user to implement a power/signal noise robust layout design through the shortest connection in the vertical channels for power routing and a SerDes high-speed interface as well as no cross pattern, and less jog and vias in the horizontal memory channels.

Are you still doing manual silicon interposer routing? Would you like to find a better alternative?