Blog Review: Aug. 14

Internet trends; financial cybersecurity; reducing NN size; solder joint failure.


Cadence’s Paul McLellan digs into Mary Meeker’s analysis of Internet trends, from growth of the Inernet as a whole to cyber attacks, online finance, and the gig economy.

Synopsys’ Taylor Armerding warns that the financial services industry is aware of cybersecurity threats, but isn’t doing enough to protect its networks and data.

Mentor’s Colin Walls considers a few cases where writing in a high level language like C or C++ may be preferable to using assembly language.

Arm’s Charlotte Christopherson points to two projects trying to reduce the complexity and size of neural networks to allow them to run on power- and compute-limited devices.

ANSYS’ Tyler Ferris diagnoses the five most common reasons for solder joint failure, from stresses caused by potting and other encapsulants to PCBA over-constraint conditions like component mirroring.

SEMI’s Emmy Yi checks out the burgeoning market for flexible hybrid electronics, with insight from industry experts on what’s next for things like smart clothing, wearables, and foldable smartphones.

A Rambus writer points to a new strain of malware, called Silex, that attacks IoT devices using default or weak credentials then trashes the device’s storage, firewall rules, and network configuration to make it appear bricked.

Lam Research’s Sharma Pamarthy takes a look at ways old equipment can be repurposed to new tasks with the example of a reactive-ion etch machine released 10-15 years ago getting updated for new GaN wafers.

And check out the blogs highlighted in the recent Low Power-High Performance newsletter:

Editor In Chief Ed Sperling finds that more data and new applications are driving demand for performance once again.

Mentor’s Durgesh Prasad, Jitesh Bansal, and Madhur Bhargava explain the differences between RTL UPF and gate-level UPF, and why it is important to create files that require minimal changes when re-used.

Fraunhofer EAS’s Benjamin Prautsch demonstrates why generators for schematics, test benches, simulation control, and layouts can significantly increase efficiency in the various design phases.

Synopsys’ Jamileh Davoudi advises that the earlier functional safety analysis is performed in the design cycle, the higher the chance of identifying hotspots and meeting target ASIL.

Adesto’s Apurba Pradhan observes that when disconnected silos of automation can share data, efficiencies can be gained.

OneSpin’s Nicolae Tusinschi notes that successful RISC-V projects entail more than core compliance to the ISA.

Rambus’ Saman Sadr explains why it is essential to have a range of experts at various stages of a 112 Gbps SerDes design.

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