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Blog Review: Aug. 3

PCB laminate; automotive quality; CMP; 3D NAND wordline resistance; dropping phones.

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Siemens’ Patrick Hope explains the growing importance of choosing the right laminate for PCB designs and how to read a material datasheet to compare important electrical, thermal, and mechanical properties.

Synopsys’ Yankin Tanurhan argues that as the number of sensors being integrated in automotive systems increases to enable new ADAS and autonomy capabilities, building security and quality into all stages of the design’s lifecycle becomes integral.

Cadence’s Paul McLellan explains chemical mechanical planarization (CMP), the process of making wafers flatter, and some of the issues that can arise during the process such as dishing, pooling, and oxide loss.

Coventor’s Brett Lowe investigates the impact of void formation on wordline resistance in 3D NAND, which needs to be highly controlled to maintain the desired memory switching speed.

Ansys’ Alexander Pett explains explicit dynamics analysis, a time integration method used to perform dynamic simulations when speed is important, such as estimating the damage incurred when a phone is dropped.

In a podcast, Arm’s Geof Wheelwright chats with Arm’s Pablo Fraile, Unity’s Ralph Hauwert, and Sony’s Tetsuya Kimura about opportunities in the growing TV ecosystem, including what’s needed for future solutions, gaming and other interactive experiences, and there the future TV is headed.

A Brewer Science writer explores how hybrid bonding can enable higher bandwidth and increased power and signal integrity and the main differences between SiOx/metal hybrid bonding and polymer/metal hybrid bonding.

A Rambus writer suggests ways to implement Reliability, Availability, and Serviceability (RAS) mechanisms that go above and beyond those included in the PCI Express Base Specification, including error tolerance and layer-based monitoring.

Western Digital’s Ronni Shendar explores how scientists are managing to image black holes through observations from a large number of networked telescopes and the massive amounts of data required to produce previously unimaginable images.

And be sure to check out the blogs featured in the latest Systems & Design newsletter:

Editor in Chief Ed Sperling examines the CHIPS Act, concluding that while it addresses supply chain risks, it also raises significant unanswered questions.

Technology Editor Brian Bailey observes that metrics for determining completeness are both incomplete and biased in both ML and UVM.

Synopsys’ Ian Land and Ricardo Borges look at how to ensure semiconductor components will survive while orbiting our planet or traveling through deep space.

Renesas’ Marta Martínez Vázquez lays out advances in radar technology that enable more sophisticated analysis, detection, and tracking.

Cadence’s Frank Schirrmeister summarizes the rapid changes happening in the aerospace/defense ecosystem.

Siemens EDA’s Dina Medhat uses a systematic methodology to verify latch-up prevention and ESD protection of 2.5D and 3D ICs.

Movellus’ Aakash Jani warns that the clock distribution network consumes a sizable portion of the physical design and verification budget.

Codasip’s Brett Cline finds enthusiastic support for the RISC-V ISA as architectural innovation takes over from traditional scaling.

Synopsys’ Ricardo Borges and Anand Thiruvengadam explain why optimizing memory at advanced nodes requires it to be designed in the context of other technology.

Keysight’s Don Dingee offers techniques for smoothing out friction in a connected RF workflow.

Siemens EDA’s WeiLii Tan and Jeff Dyck look at utilizing ML to produce consistent, verifiable, and correct answers for SPICE-level IC verification.



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