Blog Review: Dec. 20

RISC-V processor trace; PCIe 6.0 optimizations; photonics in multi-die systems.


Siemens’ Huw Geddes finds that the flexibility offered by the RISC-V ISA can introduce further verification and validation requirements to ensure that the combination of extensions and customization not just works but does not break anything else while delivering expected performance, plus looks at how processor trace can help.

Cadence’s Gustavo Araujo explains the various optimizations in the PCIe 6.0 specification that were introduced to enable the higher throughput rate, including loss reduction through new encoding, the flit sequence number protocol, and the ability to change link width during active data transfer.

Synopsys’ Kenneth Larsen and Twan Korthorst suggest that integrating photonic components into multi-die systems can offer an answer to greater demands for bandwidth and density of next-generation chips while mitigating heat dissipation and energy consumption concerns.

Arm’s Annie Tallund shows how to analyze and optimize machine learning model performance on Arm IP using the ML Inference Advisor tool.

In a blog for SEMI, Tobias Egle and Sarah Luppino of M Ventures and Jennifer Ard and Alexandra Farmer of Intel Capital introduce a program for startup companies with innovations that can help improve the sustainability of the semiconductor value chain through better management of water, materials, energy, and emissions.

Rambus’ Steven Woo shares highlights from Supercomputing 2023, including the development of the Frontier system and the challenge and necessity of scaling energy efficiency.

Ansys’ David Schneider introduces metamodels, or models of models, and how they can be used alongside AI/ML to run simulations faster, explore broader design possibilities, and reduce development costs.

Keysight’s Emily Yan suggests using artificial neural networks for semiconductor device modeling to create accurate models more quickly.

Renesas’ Prabhath Horagodage shows how combining different power-saving functions available in microcontrollers can drastically reduce power consumption.

Plus, check out the blogs featured in the latest Low Power-High Performance and Manufacturing, Packaging & Materials newsletters:

Quadric’s Steve Roddy explains how to create your own benchmark models for NPU vendor evaluation.

Rambus’ Steven Woo looks at how power consumption is optimized in the world’s most powerful supercomputers.

Fraunhofer IIS/EAS’ André Schneider, Olaf Enge-Rosenblatt, and Björn Zeugmann describe efforts to match AI algorithms to the right hardware and software platforms.

Synopsys’ Robert Ruiz shows how to gain a holistic view of verification progress without the manual effort.

Keysight’s Sarah LaSelva looks at how to capture transient events more efficiently with a source/measure unit.

Cadence’s Jasmine Jasmine lays out a way to create a simplified thermal model that still accurately accounts for the details in each layer.

Ansys’ David Campbell checks out the process of enhancing the performance of hydrogen electrolyzers that use renewable energy sources.

Calibra’s Jan Willis shared insights from the SPIE Photomask Technology Conference, including the factors driving 193i lithography down to smaller nodes.

Amkor’s DaeYoung Park explains how to achieve high package integration with routable leads and high heat dissipation.

Lam Research’s Jacky Huang shows how a virtual fabrication platform can be used to identify DRC violations and potential failures faster and cheaper than silicon wafer-based experimentation.

Synopsys’ Vivek Jain discusses how fabs can maximize efficiency with Industry 4.0 and AI/ML.

SEMI’s Cassandra Melvin highlights speeches from the CEO Summit during SEMICON Europa 2023, noting that the path to US$1 trillion in chip revenues must align with global net zero commitments.

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