Blog Review: Jan. 20

Siemens EDA’s Harry Foster takes a look at the amount of time IC and ASIC projects spend in verification, changes in the number of engineers on a project, and how engineers are spending their time.

Synopsys’ Stelios Diamantidis considers the importance of specialized accelerators for AI workloads as both cloud and edge push the PPA limits of current technologies.

Cadence’s Paul McLellan predicts that this year there will be more testing for autonomous driving, wearables featuring more medical sensors, and security concerns going more mainstream.

Arm’s Tim Thornton and Kushal Koolwal explain how the company took its EDA tools to the cloud and the journey of designing the Cortex-M55 CPU from on-prem to Arm Neoverse based AWS Graviton2 processors.

A Rambus writer highlights DRAMSys4.0, a flexible and fast DRAM subsystem design exploration framework based on SystemC TLM-2.0 and designed to address the challenges of different DRAM architectures.

Ansys’ Sandra Gély, Shailesh Ozarkar, and Kai Zhou look at ways to reduce the impact bad weather such as rain, fog, and snow has on the sensors ADAS and autonomous vehicles rely upon.

In a video, VLSI Research’s Dan Hutcheson and Andrea Lati chat about the surprisingly good year for the semiconductor industry in 2020 and the forecast for the coming year, including the strong growth driven by China and the potential for shortages later in the year.

SEMI’s Serena Brischetto chats with Elisabeth Brandl of EV Group about trends and new developments within the power electronics industry and the transition from silicon to compound semiconductor materials such as silicon carbide and gallium nitride.

A Xilinx writer offers predictions for 2021, including the importance of AI in 5G, deployment of SmartNICs in data centers, a rise in domain-specific architectures, and expanded telehealth services.

And don’t miss the blogs featured in the latest Low Power-High Performance newsletter:

Siemens’ John Parry and Wendy Luiten explain why it’s important to use both simulation and testing to improve reliability and productivity in digital designs.

Rambus’ John Eble lays out what to expect from the next generation of server memory.

Arm’s Rob Aitken describes efficiency gains that can be boosted by combining CPUs, NPUs, GPUs, and networking processors in novel ways.

Synopsys’ Priyank Shukla details how the latest architectural shift has significant implications for simulation and modeling of high-speed SerDes transceivers.

Cadence’s Paul McLellan shines a light on the path forward for EUV and the new transistor types needed to reach 1nm.

Ansys’ Theresa Duncan and Craig Hillman untangle a new standard for reliability physics analysis of electrical, electronic, and electromechanical components.