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Blog Review: Jan. 26

Securing hardware; RISC-V ecosystem; multi-discipline environments; PCIe 6.0.

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Arm’s Mark Inskip shares how the Morello prototype architecture, aimed at improving the security of hardware, was developed, from the creation of the prototype architecture specification, followed by the design and implementation of a new CPU, through to the development of a new SoC, hardware platform, development tools, toolchains, and software.

Cadence’s Paul McLellan looks at how the RISC-V ecosystem is managing to hold fragmentation at bay, why there are many ISAs used on one SoC, and RISC-V adoption in industry.

Siemens’ Katie Tormala argues that when distributed teams use a multi-discipline collaborative environment that integrates mechanical, electrical and software domains, they can work together more efficiently and streamline product development.

A Synopsys writer highlights the changes in PCIe 6.0 that enable a doubling of bandwidth with 64GT/s raw data rate physical layer enabling up to 256 GB/s data transfers via 16-lane configuration.

The ESD Alliance’s Bob Smith chats with Laurie Balch of Pedestal Research about trends in EDA and IP, including the potential of open-source EDA efforts, geographic diversity, and the expansion of cloud-based design.

Ansys’ Laura Carter checks out how one autonomous shuttle company is collecting, analyzing, and demonstrating safety information to regulators and potential clients.

Coventor’s Hideyuki Maekoba checks out how earthquake monitoring is supplementing traditional sensor networks with MEMS-based seismic sensors to fill coverage holes and provide early warnings more quickly.

A Xilinx writer looks at the difference between dense TOPS and sparse TOPS and how sparsity can improve system performance.

Memory analyst Jim Handy examines Samsung’s Aquabolt-XL processor-in-memory architecture, its performance, and how it compares to other companies’ similar devices.

Plus, check out the blogs featured in the latest Manufacturing, Packaging & Materials newsletter:

Executive editor Mark LaPedus discusses the wafer market with a SEMI analyst, who sees slower growth in 2022.

Amkor’s Shaun Bowers demonstrates a new packaging format that provides extreme silicon area density versus package volume.

Coventor’s Taeyon (TY) Oh looks at why CMP erosion and dishing defects due to differences in pattern density are becoming a significant issue.

Calibra’s Jan Willis predicts that sales of new photomask writers are expected to increase across all segments.

Advanced Energy’s Peter Gillespie contends that it’s time to re-think how power is managed in plasma-based applications.

Lam Research’s Tim Archer foresees meeting the global talent shortage through diversity and inclusion.

Brewer Science’s Jessica Albright argues for reducing the environmental impact of manufacturing.



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