Blog Review: May 2

Arm’s Greg Yeric looks towards the future of 3D ICs with a dive into transistor-level 3D, including the different proposed methods of stacking transistors, power/performance benefits, and challenges such as parasitic resistance.

Mentor’s Kurt Takara, Chris Kwok, Dominic Lucido, and Joe Hupcey III explain how a custom synchronizer methodology can help avoid CDC mistakes and errors in FPGA designs by adding protective logic, specifying assumption checks, and declaring CDC library structures.

Cadence’s Paul McLellan listens in as renowned security experts discuss quantum computing and cryptography, the Spectre vulnerability, and where there are silver linings in security today.

Synopsys’ Meenakshy Ramachandran takes a look at HDMI 2.1 with a specific focus on VESA Display Stream Compression and how it enables 10k displays.

Intel’s Ron Wilson dives into neuromorphic computing with an examination of what it is, how neuromorphic networks differ from convention deep learning networks, and where possible applications may lie.

Aldec’s Vatsal Choksi explains randomized layered testbenches used in SystemVerilog and why they’re an improvement over Verilog/VHDL direct testing oriented testbenches.

Rambus’ Aharon Etengoff check out NIST’s new initiative aimed at developing lightweight cryptography standards to better protect sensors and other resource-constrained IoT devices.

SEMI’s Lara Chamness examines last year’s trends in the booming semiconductor equipment market and the slightly more complicated materials market, along with what to look forward to this year.

Modelithics’ Isabella Bedford argues that as wireless technology moves to smaller scales and more compact designs, 3D modeling in electromagnetic analysis is a crucial step in circuit design flows.

Lam Research’s Elizabeth Pavel points to the ways technology is helping in the conservation and restoration of classic artworks, from varnish composition analysis to pinpointing damage.

Silicon Labs’ Lance Looper considers the possible threats IoT devices will face and argues that they will require the ability to be securely updated, which comes with its own set of challenges.

Nvidia’s Tony Kontzer points to an application of image recognition AI that aims to help blind and low-vision users more easily navigate the world.

And don’t forget to check out the blogs featured in last week’s System-Level Design newsletter:

Editor In Chief Ed Sperling argues that it’s too early to predict who will win and why, but there are big opportunities emerging everywhere.

Mentor’s James Paris shows why it’s so important to validate chip-level interconnects and block interfaces early.

Arteris IP’s Kurt Shuler explains why interconnects are vital when incorporating deep learning into automotive designs.

UltraSoC’s Gajinder Panesar digs into the world of servers and high-performance computing, where the smallest inefficiencies can build into big problems.

Aldec’s Vatsal Choksi examines the different phases that UVM follows.

OneSpin’s Tom Anderson observes that equivalence checking was key to making logic synthesis mainstream, but it’s more complex when it comes to FPGAs.

eSilicon’s Mike Gianfagna looks at why great strides in artificial intelligence and deep learning are happening now.

Synopsys’ Mark Richards views simple flows as the vestige of a bygone era.

Cadence’s Frank Schirrmeister contends that tradeoffs can be a good thing when you have the flexibility to choose what’s important.

Technology editor Brian Bailey considers why artificial intelligence will change our views, and why you need to know that.

Coventor’s Yu De Chen, Jacky Huang, Dalong Zhao, Jiangjiang (Jimmy) Gu, and Joseph Ervin look at how design technology co-optimization improves yield and accelerates time to market.

The University of Michigan’s Valeria Bertacco points out DAC’s must-see technical sessions this June in San Francisco.

Semico Research’s Joanne Itow notes that while Artificial Intelligence still can’t compete with common sense, its usefulness is growing quickly.