Blog Review: Nov. 30

Cadence’s Sangeeta Soni explores how the configuration space for CXL 1.1 and CXL 2.0 varies and discusses newly introduced registers for the CXL-compliant devices and how they are discovered during the CXL enumeration flow.

Siemens EDA’s Harry Foster continues examining trends in FPGA verification effort by looking at where both design and verification engineers spend their time.

Synopsys’ Emilie Viasnoff finds that digital twins and image simulation can enable better, more streamlined specifications and virtual testing of cameras and imaging systems.

Ansys’ Matt Adams explains how to build hybrid digital twins that combine both physics and data using hybrid analytics techniques such as fusion modeling that uses multiple different types of data to train a machine learning model.

Renesas’ Kayoko Nemoto looks at the networking technology that will help enable Industry 4.0 through local control area networks that provide a digital link between controllers and smart sensors, actuators, and transducers that can go in both directions and industrial Ethernet that provides determinism and real-time control.

SEMI’s James Amano examines European Union cybersecurity and AI regulations that could impact semiconductor industry, including new criteria for AI used in machinery safety components as well as cybersecurity regulation of products with digital elements that have a logical or physical data connection to a device or network.

Arm’s Khaled Benkrid and Nick Sample consider the many dimensions of diversity and inclusion and how a lack of DEI efforts in the education pipeline is contributing to a skills shortage in technology fields.

Eindhoven University of Technology’s Erwin Kessels finds that the manufacturing steps of deposition, lithography, and etching are merging, leading to both added complexity and new opportunities, and shares some resources on the use and evolution of low-temperature plasmas in semiconductor fabrication.

For a change from reading, watch some recent videos:

An interoperability layer is essential to tracking and Managing IP In Heterogeneous Designs.

Automated Optical Inspection shows how machine learning is used to improve manufacturing quality.

Access to dies or chiplets is problematic, but a new standard may help with Testing 2.5D And 3D-ICs.

Heterogeneous Integration Issues And Developments explores why putting different chips and chiplets into a package is harder than it sounds.

Why Changes In Computing Are Driving Changes In Photomasks and how different photomask shapes can improve semiconductor reliability and performance.

What the new version of high-bandwidth memory will bring, and where the challenges are when using HBM3 In The Data Center.

Simplifying AI Edge Deployment depends on keeping device models up to date while optimizing power and performance.

Longer chip lifetimes mean they need to adapt to security threats, but Using eFPGAs For Security could help.

Why Quantum Computing has taken so long to materialize, and what’s still missing.

Access IP information quickly over longer chip and package lifetimes by Boosting Data Management System Performance.