Low Power Trends Toward FinFET
By Mary Ann White - 12 Feb, 2015 - Comments: 0

My previous blog, Power Reduction Techniques, covered which low power techniques were applicable for various process nodes, from larger planar CMOS process technologies through finFET. The 16 and 14nm finFET-based process nodes are moving into production this year, and we are seeing many companies rapidly move their designs to finFET. In my last post, I noted some of the reasons why finFET is s... » read more

Applying Lessons Of Mass Production To Verification
By Larry Vivolo - 12 Feb, 2015 - Comments: 0

I’ve recently been experiencing that time-honored tradition of helping an elderly family member as they go through one surgery after another attempting to restore worn-out, miscellaneous body parts. What’s most surprising, beyond the costs, is that shopping for a knee or disc replacement is much like shopping for a car. Do you go for the high-performance knee, which maybe hasn’t been test... » read more

Low-Power Design Is More Than Just Minimizing Power
By Muhammad Zakir - 12 Feb, 2015 - Comments: 0

Engineers are accustomed to making tradeoffs when designing products — faster and more power-hungry, or slower and lower-power; expensive and durable, or cheap and disposable; and so on. The ongoing list of tradeoffs and subsequent choices that need to be made can sometimes appear quite daunting. This blog discusses how the design of electronic systems in the context of power has expanded bey... » read more

Reliability Definition Is Changing
By Ed Sperling - 12 Feb, 2015 - Comments: 0

Since the invention of the integrated circuit, reliability has been defined by how long a chip continues to work. It either turned on and did what it was designed to do, or it didn't. But that definition is no longer so black-and-white. Parts of an SoC, or even an IP or memory block, can continue to function while other parts do not. Some may work intermittently, or at lower speeds. Others may ... » read more

Accellera Adds Portable Stimulus Group
By Brian Bailey - 11 Feb, 2015 - Comments: 0

[getentity id="22028" e_name="Accellera"] created a working group for the portable test and stimulus, which would allow engineering teams to create the test once and be able to run it throughout the flow. This is a big deal in verification because it allows horizontal reuse of a [getkc id="55" kc_name="testbench"]. Test patterns run on the processors in a design and that enables the test to ... » read more

Blog Review: Feb. 11
By Jesse Allen - 11 Feb, 2015 - Comments: 0

Ansys' Bill Vandermark flags the top five engineering articles of the week. Check out the one about the latest attempt at cold fusion, which left researchers hiding behind a blast shield. The solar-powered car named Stella drove away with the prestigious "Best Technology Achievement" award at the 8th annual Crunchies Awards this week. NXP's Maurice Geraets sounds like a proud parent – with... » read more

Advanced Power And Performance Optimization For Multicore SoCs
By Synopsys - 11 Feb, 2015 - Comments: 0

The Multicore Optimization (MCO) technology in Synopsys Platform Architect provides an environment for early exploration and optimization of complex Multicore SoC (MP-SoC) platforms. It allows quantitative analysis of performance and power metrics to avoid SoC market failure due to underperforming or power hungry architectures. To read more, click here. » read more

Leveraging Physically Aware Design-For-Test To Improve Area, Power, And Timing
By Cadence - 11 Feb, 2015 - Comments: 0

Increased pressures on design teams to deliver faster, smaller devices in less time has required EDA companies to develop an integrated methodology to incorporate physical design information during DFT synthesis. This solution must consider the placeable area (or size) of the circuit as well as routing blockages and hard macro placement locations. It must also be able to both model the wiring i... » read more

Optimizing Emulator Utilization
By Mentor, a Siemens Business - 11 Feb, 2015 - Comments: 0

Russ Klein describes how Codelink, a Mentor Graphics trace-based debug tool, gives software developers a traditional software debug view from a unique processor trace, enabling them to increase emulator utilization and enjoy a more productive debug experience. Codelink allows for software debug earlier in the design cycle, as it makes it possible to use the emulator without having debug circuit... » read more

One-On-One: Walid Abu-Hadba
By Ed Sperling - 11 Feb, 2015 - Comments: 0

Walid Abu-Hadba, chief product officer at [getentity id="22021" e_name="Ansys"] (and a former top executive at Microsoft), sat down with Semiconductor Engineering to talk about systems engineering and why the starting point is no longer the SoC. What follows are excerpts of that conversation. SE: How do you define system? Abu-Hadba: It's everything. It's the entire product and where the p... » read more

← Older posts Newer posts →

  • Sponsors

About

Navigation

Connect With Us

Copyright ©2013-2025 SMG   |  Terms of Service  |  Privacy Policy