Measurement-Induced Quantum Information Phases On Up To 70 Superconducting Qubits (Google/Stanford)


A technical paper titled “Measurement-induced entanglement and teleportation on a noisy quantum processor” was published by researchers at Google Quantum AI, Google Research, Stanford University, University of Texas at Austin, Cornell University, University of Massachusetts, University of Connecticut, Auburn University, University of Technology Sydney, University of California, and Columbia... » read more

Discovering Orbital Multiferroicity in Pentalayer Rhombohedral Graphene (MIT)


A technical paper titled “Orbital Multiferroicity in Pentalayer Rhombohedral Graphene” was published by researchers at Massachusetts Institute of Technology. Abstract (partial): "Ferroic orders describe spontaneous polarization of spin, charge, and lattice degrees of freedom in materials. Materials featuring multiple ferroic orders, known as multiferroics, play important roles in multi-fu... » read more

Research Bits: October 24


Photonic-electronic hardware processes 3D data Researchers from the University of Oxford, University of Muenster, University of Heidelberg, and University of Exeter are developing integrated photonic-electronic hardware capable of processing three-dimensional data, which the team claims boosts data processing parallelism for AI tasks. The researchers added an extra parallel dimension to the... » read more

Chip Industry’s Technical Paper Roundup: October 24


New technical papers added to Semiconductor Engineering’s library this week. [table id=157 /] More Reading Technical Paper Library home » read more

DSP Techniques For High-Speed SerDes


Sensors everywhere, more connected devices, and the rollout of smart everything has created a flood of data. The question now is how to best handle all of that data, where to process it, and how to move it locally and to the outside network. Madhumita Sanyal, technical product manager at Synopsys, talks about the need for continuous performance improvements in SerDes, PCIe, NRZ, and PAM4, and w... » read more

Gearing Up For Hybrid Bonding


Hybrid bonding is becoming the preferred approach to making heterogeneous integration work, as the semiconductor industry shifts its focus from 2D scaling to 3D scaling. By stacking chiplets vertically in direct wafer-to-wafer bonds, chipmakers can leapfrog attainable interconnection pitch from 35µm in copper micro-bumps to 10µm or less. That reduces signal delay to negligible levels and e... » read more

Chip Industry Week In Review


By Susan Rambo, Gregory Haley, and Liz Allan SRC unfurled its Microelectronics and Advanced Packaging (MAPT) industry-wide 3D semiconductor roadmap, addressing such topics as advanced packaging, heterogeneous integration, analog and mixed-signal semiconductors, energy efficiency, security, the related foundational ecosystem, and more. The guidance is the collective effort of 300 individuals ... » read more

Energy Usage in Layers Of Computing (SLAC)


A technical paper titled “Energy Estimates Across Layers of Computing: From Devices to Large-Scale Applications in Machine Learning for Natural Language Processing, Scientific Computing, and Cryptocurrency Mining” was published by researchers at SLAC National Laboratory and Stanford University. Abstract: "Estimates of energy usage in layers of computing from devices to algorithms have bee... » read more

A Study Of LLMs On Multiple AI Accelerators And GPUs With A Performance Evaluation


A technical paper titled “A Comprehensive Performance Study of Large Language Models on Novel AI Accelerators” was published by researchers at Argonne National Laboratory, State University of New York, and University of Illinois. Abstract: "Artificial intelligence (AI) methods have become critical in scientific applications to help accelerate scientific discovery. Large language models (L... » read more

FeFET Multi-Level Cells For In-Memory Computing In 28nm


A technical paper titled “First demonstration of in-memory computing crossbar using multi-level Cell FeFET” was published by researchers at Robert Bosch, University of Stuttgart, Indian Institute of Technology Kanpur, Fraunhofer IPMS, RPTU Kaiserslautern-Landau, and Technical University of Munich. Abstract: "Advancements in AI led to the emergence of in-memory-computing architectures as a... » read more

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