Innovate Faster with A Multi-Die Solution
By Synopsys - 13 Nov, 2024 - Comments: 0

The semiconductor industry is experiencing a monumental shift in chip design, driven by the dramatic increase in AI compute performance requirements and limitations of Moore’s Law. The industry is adopting multi-die designs, which is the heterogeneous or homogeneous integration of dies (also called chiplets) in a single package. While multi-die design is the solution, it also introduces se... » read more

Systems-in-Package: Authenticated Partial Encryption Protocol For Secure Testing (U. of Florida)
By Technical Paper Link - 12 Nov, 2024 - Comments: 0

A new technical paper titled "GATE-SiP: Enabling Authenticated Encryption Testing in Systems-in-Package" was published by researchers at University of Florida and University of Central Florida. Abstract: "A heterogeneous integrated system in package (SIP) system integrates chiplets outsourced from different vendors into the same substrate for better performance. However, during post-integra... » read more

Getting The Biggest ROI On Your Digital Twin
By Sean King - 12 Nov, 2024 - Comments: 0

In the semiconductor industry, digital twins are the focus of a lot of attention, with substantial investments from industry players and governments alike. This year the European Union and the United States have pledged hundreds of millions of dollars in grants and funding opportunities, including the new CHIPS Digital Twin Manufacturing USA Institute. Ultimately, many people see great value in... » read more

Extending Chip Lifetime With Safer Voltage Scaling
By Eyal Fayneh - 12 Nov, 2024 - Comments: 0

What if your chips lived 20% longer without compromising performance, and even while reducing power consumption? How would it affect your product’s reliability and cost? What would be the effect on your profitability? With the demand for longer-lasting chips growing across industries, designers and reliability engineers face increasing pressure to ensure their products perform correctly fo... » read more

Power-Aware Test Vector Porting For Production ATE
By Hari Mani - 12 Nov, 2024 - Comments: 0

Power management in contemporary system-on-chip (SoC) designs is almost unimaginably complex. Processors and other chip cores turn on and off as needed. Advanced features such as dynamic voltage and frequency scaling (DVFS) can adjust to changing conditions and incrementally adjust power and performance on the fly. Power management starts from the lowest hardware level of transistor structures ... » read more

AI’s Ability To Deliver Breakthroughs Across Semiconductor Design And Manufacturing
By John Kibarian - 12 Nov, 2024 - Comments: 0

AI holds great promise for our industry. It will help close the divide between design, manufacturing and test that is required to effectively produce today’s most advanced hybrid devices. One way to look at the potential impact of AI in the semiconductor industry is to realize that it is more and more driven by software engineering. When designing a chip, it’s essentially like writing... » read more

Advanced Packaging Drives Test And Metrology Innovations
By Gregory Haley - 12 Nov, 2024 - Comments: 1

Advanced packaging has become a focal point for innovation as the semiconductor industry continues to push for increased transistor density and better performance. But the pace of change is accelerating, making it harder for the entire ecosystem to keep up with those changes. In the past, major developments were roughly on an 18-month to 2-year cadence. Today, this is happening every few mon... » read more

Yield Management Embraces Expanding Role
By Laura Peters - 12 Nov, 2024 - Comments: 0

Competitive pressures, shrinking time-to-market windows, and increased customization are collectively changing the dynamics and demands for yield management systems, shifting left from the fab to the design flow and right to assembly, packaging, and in-field analysis. The basic role of yield management systems is still expediting new product introductions, reducing scrap, and delivering grea... » read more

Balancing Parallel Test Productivity With Yield & Cost
By Anne Meixner - 12 Nov, 2024 - Comments: 0

Parallel test is used for nearly every device produced by fabs and OSATs, but it can reduce yield and increase the cost of test boards and operations. This is a well-understood tradeoff for ensuring consistent test accuracy across multiple sites and reducing test time. Collectively, ATEs and multi-site test boards — DUT interface boards (DIBs), probe cards, and load boards — significantl... » read more

FTIR Detects Counterfeit Electronics
By Inga Koehler - 12 Nov, 2024 - Comments: 0

FTIR spectroscopy detects counterfeit electronics fast and effectively.[1] It provides a critical solution in the fight against counterfeit products that threaten various sectors of our economy. As counterfeits infiltrate industries like fashion, pharmaceuticals, and luxury goods, they pose serious risks. With the advancement of technology, counterfeit components in electronics are becom... » read more

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