Improved DSP And AI Performance On An MCU Core
By Eldar Sido - 27 Apr, 2023 - Comments: 0

In the world of embedded devices, there's a growing demand for advanced machine learning and signal processing capabilities. ARM Cortex-M85, the latest general-purpose core, aims to meet these demands with its 32-bit Armv8.1-M architecture, offering high performance and power efficiency. The core's Helium technology, M-profile vector extension (MVE), provides significant uplift for ML/DSP appl... » read more

Notes From CadenceLIVE Silicon Valley 2023
By Paul McLellan - 27 Apr, 2023 - Comments: 0

Last week was CadenceLIVE Silicon Valley, held at the Santa Clara Convention Center, and took place, as usual, over two days. It was very well attended and everywhere seemed fairly crowded. The structure of CadenceLIVE was that the first morning was taken up with four keynotes. Then the rest of the day and all of the following day were taken up with about ten parallel technical tracks. And at l... » read more

Hardware-Accelerated RTL Simulator
By Technical Paper Link - 26 Apr, 2023 - Comments: 0

A technical paper titled "Manticore: Hardware-Accelerated RTL Simulation with Static Bulk-Synchronous Parallelism" was published by researchers at EPFL, University of Tokyo, Sharif University, and Indian Institute of Technology. Abstract "The demise of Moore's Law and Dennard Scaling has revived interest in specialized computer architectures and accelerators. Verification and testing of thi... » read more

Information flow policies for NVM Technologies
By Technical Paper Link - 26 Apr, 2023 - Comments: 0

A new technical paper titled "Automated Information Flow Analysis for Integrated Computing-in-Memory Modules" was published by researchers at RWTH Aachen University. Abstract: "Novel non-volatile memory (NVM) technologies offer high-speed and high-density data storage. In addition, they overcome the von Neumann bottleneck by enabling computing-in-memory (CIM). Various computer architectures... » read more

RISC-V Vectorization And Potential for HPC
By Technical Paper Link - 26 Apr, 2023 - Comments: 0

A new technical paper titled "Test-driving RISC-V Vector hardware for HPC" was published by researchers at University of Edinburgh. Abstract: "Whilst the RISC-V Vector extension (RVV) has been ratified, at the time of writing both hardware implementations and open source software support are still limited for vectorisation on RISC-V. This is important because vectorisation is crucial to obt... » read more

Overview Of EV Charging Infrastructure, The Role of Power Electronics, And Charging Technologies
By Technical Paper Link - 26 Apr, 2023 - Comments: 0

A technical paper titled "Charging Infrastructure and Grid Integration for Electromobility" was published by researchers at Universidad de los Andes, University of Cambridge, Duke University, Universidad Técnica Federico Santa Maria, University of Toronto, TU Delft, and University of Florence. Abstract "Electric vehicle (EV) charging infrastructure will play a critical role in decarbonizat... » read more

New Standards Push Co-Packaged Optics
By Karen Heyman - 26 Apr, 2023 - Comments: 0

Co-packaged optics (CPOs) promise five times the bandwidth of pluggable connections, but the new architecture requires multiple changes to accommodate different applications. The Optical Internetworking Forum (OIF) recently published standards for co-packaged optics, which are the photonic industry’s hope for handling today’s faster Ethernet interfaces, as well as increasing speeds and p... » read more

Pre-Layout, Post-Layout Circuit Reliability
By Siemens EDA - 26 Apr, 2023 - Comments: 0

With the increasing complexity of design layouts and shorter tapeout cycles, waiting until signoff verification to check design reliability is no longer practical for design teams. Designers must now apply reliability verification checks throughout the design flow, from intellectual property (IP) level to full-chip level, to ensure they meet tapeout schedules while confirming design reliability... » read more

Impacts Of Process Flow, Scaling, And Variability On Interconnect Performance
By Lam Research - 26 Apr, 2023 - Comments: 0

Virtual fabrication is used to evaluate the performance of interconnects (line and via resistance, capacitance, etc.) across pitches compatible with either EUV single exposure or SADP for three different process flows: single damascene, dual damascene, and semi-damascene (subtractive metal etch). The effects of process variation for the three flows are also investigated to determine the relativ... » read more

Meeting The Major Challenges Of Modern Memory Design
By Synopsys - 26 Apr, 2023 - Comments: 0

Memory lies at the heart of every electronics application, and demand is growing all the time. Users want ever greater capacity, throughput, and reliability. At the same time, time to market (TTM) goals and competitive pressures mandate that memories be developed in ever shorter project schedules. These requirements put enormous pressure on designers of discrete memory chips, memory dies in 2.5... » read more

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