How The Electronics Industry Can Shape A More Sustainable, Energy-Efficient World


By Piyush Sancheti and Godwin Maben We’re already experiencing the effects of our world’s changing climate—devastating wildfires, prolonged droughts, torrential flooding, just to name a few examples. Global energy consumption is increasing, raising carbon dioxide levels and triggering extreme weather conditions. Two key forces driving these trends are the shift to hyperscale datacenter... » read more

Extending RISC-V Processors In The Field With Codasip Studio & Menta eFPGA


RISC-V is an open specification that allows an infinite number of implementations. But RISC-V goes beyond that and encourages processor architects to add new instructions to accelerate certain algorithms or application domains, for example DSP, AI/ML, and others, while keeping the base instruction set stable. The new instructions may help with the performance, code size, power consumption, or d... » read more

Speed Up Early Design Rule Exploration And Physical Verification


Ensuring that early-stage IC design physical verification actually enhances IC design and verification productivity means giving engineers the ability to focus on those errors that are both valid and critical in early-stage designs. The Calibre nmDRC Recon functionality provides selective DRC of early-stage designs that focuses on real, relevant errors, ignoring rule checks that generate meanin... » read more

IEDM Keynote: Ann Kelleher On Future Technology


IEDM 2022 celebrated 75 Years of the Transistor. I can't imagine anything else invented in the last 75 years has had as much effect on my life, and probably yours, too. After the awards session, the conference got underway with a keynote by Ann Kelleher, Executive Vice President and General Manager of Technology Development at Intel. It was titled "Celebrating 75 Years of the Transistor! A L... » read more

Accelerate The Algorithm To Silicon Development With Stratus HLS


Growth in demand for artificial intelligence (AI) and digital signal processing (DSP) applications, coupled with advances in semiconductor process technology, drives increasingly denser SoCs. These complex SoCs further challenge the design team’s ability to meet performance, power, and area (PPA) goals within tight time-to-market windows. We need automated and targeted solutions that efficien... » read more

Enable Application Design Without Considering Device Configuration


The software-defined vehicle, which defines in-vehicle value through software, requires new applications to be deployed in a variety of vehicle models. To achieve this, developers need a solution that allows them to easily develop applications without considering device configuration in the ECU and to take maximum performance of the hardware. However, there are currently issues (figure 1). W... » read more

MOVPE Grown (100) Beta-Gallium Oxide Layers for Power Electronics Application


A technical paper titled "Perspectives on MOVPE-grown (100) β-Ga2O3 thin films and its Al-alloy for power electronics application" was published by researchers at Leibniz-Institut für Kristallzüchtung (IKZ), Germany. "Beta gallium oxide (β-Ga2O3) is a promising ultra-wide bandgap semiconductor with attractive physical properties for next-generation high-power devices, radio frequency ele... » read more

Rowhammer Mitigation: In-DRAM Mechanism Scaling The Number of Refreshes With Activations (ETH Zurich)


A technical paper titled "REGA: Scalable Rowhammer Mitigation with Refresh-Generating Activations" was written by researchers at Computer Security Group (COMSEC), ETH Zurich and Zentel Japan. The paper will be presented at IEEE's Symposium on Security and Privacy in May 2023. "With REGA, we propose the first fully in-DRAM mitigation capable of protecting devices independently from their blas... » read more

Hardware Accelerator For Fully Homomorphic Encryption


A technical paper titled "CraterLake: A Hardware Accelerator for Efficient Unbounded Computation on Encrypted Data" was published by researchers at MIT, IBM TJ Watson, SRI International, and University of Michigan. "We present CraterLake, the first FHE accelerator that enables FHE programs of unbounded size (i.e., unbounded multiplicative depth). Such computations require very large cipherte... » read more

Efficient Gated Clock Design Approach for LFSR


A technical paper titled "A Novel Clock Gating Approach for the Design of Low-Power Linear Feedback Shift Registers" was published by researchers at Università degli Studi di Catania, Italy. Abstract "This paper presents an efficient solution to reduce the power consumption of the popular linear feedback shift register by exploiting the gated clock approach. The power reduction with respec... » read more

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