Data Filtering Directly Within A NAND Flash Memory Chip


A technical paper titled “Search-in-Memory (SiM): Reliable, Versatile, and Efficient Data Matching in SSD's NAND Flash Memory Chip for Data Indexing Acceleration” was published by researchers at TU Dortmund, Academia Sinica, and National Taiwan University. "This paper introduces the Search-in-Memory (SiM) chip, which demonstrates the feasibility of performing data filtering directly with... » read more

Dual Graphite-Gated BLG As Platform for Cryogenic FETs


A technical paper titled “Ultra-steep slope cryogenic FETs based on bilayer graphene” was published by researchers at RWTH Aachen University, Forschungszentrum Julich, National Institute for Materials Science (Japan), and AMO GmbH. "Here, we show that FETs based on Bernal stacked bilayer graphene encapsulated in hexagonal boron nitride and graphite gates exhibit inverse subthreshold slop... » read more

Chip Industry Technical Paper Roundup: August 13


New technical papers recently added to Semiconductor Engineering’s library: [table id=249 /] More ReadingTechnical Paper Library home   » read more

Research Bits: Aug. 13


3D X-ray of chip interiors Researchers from the Paul Scherrer Institute, EPFL Lausanne, ETH Zurich, and the University of Southern California used X-rays to take non-destructive, three-dimensional images of the inside of a microchip at 4 nanometer resolution. To create the images, the researchers relied on a technique called ptychography, in which a computer combines many individual images ... » read more

CPU Performance Bottlenecks Limit Parallel Processing Speedups


Multi-core processors theoretically can run many threads of code in parallel, but some categories of operation currently bog down attempts to raise overall performance by parallelizing computing. Is it time to have accelerators for running highly parallel code? Standard processors have many CPUs, so it follows that cache coherency and synchronization can involve thousands of cycles of low-le... » read more

Fantastical Creatures


In my day job I work in the High-Level Synthesis group at Siemens EDA, specifically focusing on algorithm acceleration. But on the weekends, sometimes, I take on the role of amateur cryptozoologist. As many of you know, the main Siemens EDA campus sits in the shadow of Mt. Hood and the Cascade Mountain range. This is prime habitat for Sasquatch, also known as “Bigfoot”. This weekend, ar... » read more

Chip Industry Week In Review


Three Fraunhofer Institutes (IIS/EAS, IZM, and ENAS) launched the Chiplet Center of Excellence, a research initiative to support the commercial introduction of chiplet technology. The center initially will focus on automotive electronics, developing workflows and methods for electronics design, demonstrator construction, and the evaluation of reliability. The UCIe Consortium published the Un... » read more

Challenges And Outlook Of ATE Testing For 2nm SoCs


The transition to the 2nm technology node introduces unprecedented challenges in Automated Test Equipment (ATE) bring-up and manufacturability. As semiconductor devices scale down, the complexity of testing and ensuring manufacturability increases exponentially. 3nm silicon is a mastered art now, with yields hitting pretty high for even complex packaged silicon, while the transition from 3nm to... » read more

Managing Complexity And A Left Shift: Reconfigurable Mixed-Signal Circuits For Complex Integrated Systems


By Björn Zeugmann and Benjamin Prautsch The chip market is growing worldwide; it’s projected to nearly double by 2030 to over one trillion dollars. Most of this market is made up of digital functions in the form of logic, microprocessors, and memory. Although analog ICs account for only around 15% of the total, they are key components for overall systems and are therefore almost always pr... » read more

Ensuring Multi-Die Package Quality And Reliability


Multi-die designs are gaining broader adoption in a wide variety of end applications, including high-performance computing, artificial intelligence (AI), automotive, and mobile. Despite clear advantages, there are new challenges that need to be addressed for successful multi-die realization. This article gives a high-level overview of the multi-die test challenges that go beyond the design p... » read more

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