Cadence Janus NoC System IP
By Cadence - 17 Jul, 2024 - Comments: 0

The Cadence Janus Network on Chip (NoC) is a new highly configurable soft IP designed to speed up the system-on-chip (SoC) and full system design cycle by reducing some of the problems associated with large SoCs. With many more processing nodes, as well as memory and I/O nodes designed into the SoC, the interconnect becomes a major design hurdle. Wiring congestion and wire loads introduce ch... » read more

6G And Beyond: Overall Vision And Survey of Research
By Technical Paper Link - 16 Jul, 2024 - Comments: 0

A new 92 page technical paper titled "6G: The Intelligent Network of Everything -- A Comprehensive Vision, Survey, and Tutorial" was published by IEEE researchers at Finland's University of Oulu. Abstract "The global 6G vision has taken its shape after years of international research and development efforts. This work culminated in ITU-R's Recommendation on "IMT-2030 Framework". While the d... » read more

Step Towards 3D PICs: Low Loss Fiber-Coupled Interconnects (UIUC)
By Technical Paper Link - 16 Jul, 2024 - Comments: 0

A new technical paper titled "Low loss fiber-coupled volumetric interconnects fabricated via direct laser writing" was published by researchers at University of Illinois Urbana-Champaign (UIUC). Abstract "Photonic integrated circuits (PICs) are vital for high-speed data transmission. However, optical routing is limited in PICs composed of only one or a few stacked planes. Further, coupling ... » read more

NVMs: In-Memory Fine-Grained Integrity Verification Technique (Intel Labs, IISc)
By Technical Paper Link - 16 Jul, 2024 - Comments: 0

A new technical paper titled "iMIV: in-Memory Integrity Verification for NVM" was published by researchers at Intel Labs and Indian Institute of Science (IISc), Bengaluru. Abstract "Non-volatile Memory (NVM) could bridge the gap between memory and storage. However, NVMs are susceptible to data remanence attacks. Thus, multiple security metadata must persist along with the data to protect th... » read more

In Situ Backpropagation Strategy That Progressively Updates Neural Network Layers Directly in HW (TU Eindhoven)
By Technical Paper Link - 16 Jul, 2024 - Comments: 0

A new technical paper titled "Hardware implementation of backpropagation using progressive gradient descent for in situ training of multilayer neural networks" was published by researchers at Eindhoven University of Technology. Abstract "Neural network training can be slow and energy-expensive due to the frequent transfer of weight data between digital memory and processing units. Neuromorp... » read more

Chip Industry Technical Paper Roundup: July 16
By Linda Christensen - 16 Jul, 2024 - Comments: 0

New technical papers recently added to Semiconductor Engineering’s library. [table id=244 /] More ReadingTechnical Paper Library home   » read more

Research Bits: July 16
By Jesse Allen - 16 Jul, 2024 - Comments: 0

Kirigami-inspired mechanical computer Researchers from North Carolina State University developed a kirigami-inspired mechanical computer that uses a complex structure of rigid, interconnected polymer cubes to store, retrieve, and erase data without relying on electronic components. The system uses 1-centimeter plastic cubes, grouped into functional units consisting of 64 interconnected cubes. ... » read more

EDA Revenue Up, China Weak
By Ed Sperling - 15 Jul, 2024 - Comments: 0

EDA and hardware IP revenue grew 14.4% to $4.522 billion in Q1, extending a streak that began several years ago with unabated double-digit growth. But the upbeat report masked a sharp sales drop in China for reasons that have yet to be determined. Revenue in the overall Asia/Pacific region grew a healthy 19% YoY, while China was -6.3%. The negative impact was offset by new strength in India,... » read more

Intel Vs. Samsung Vs. TSMC
By Ed Sperling - 15 Jul, 2024 - Comments: 3

The three leading-edge foundries — Intel, Samsung, and TSMC — have started filling in some key pieces in their roadmaps, adding aggressive delivery dates for future generations of chip technology and setting the stage for significant improvements in performance with faster delivery time for custom designs. Unlike in the past, when a single industry roadmap dictated how to get to the next... » read more

Monolithic 3D TFT Integration at Room Temperature, Used to Stack 10 Vertical Layers
By Technical Paper Link - 12 Jul, 2024 - Comments: 0

A new technical paper titled "Three-dimensional integrated metal-oxide transistors" was published by researchers at KAUST (King Abdullah University of Science and Technology). Abstract "The monolithic three-dimensional vertical integration of thin-film transistor (TFT) technologies could be used to create high-density, energy-efficient and low-cost integrated circuits. However, the develo... » read more

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