Research Bits: Feb. 3
By Jesse Allen - 03 Feb, 2026 - Comments: 0

Artificial synapse Researchers from Ulsan National Institute of Science and Technology (UNIST) designed a biodegradable, energy efficient artificial synapse that uses a layered structure made from naturally-derived polymers that break down naturally within 16 days in soil. "The device is built like a tiny sandwich, with ion-active layers separated by an ion-binding layer made from cellulose... » read more

Chip Industry Technical Paper Roundup: Feb. 3
By Linda Christensen - 03 Feb, 2026 - Comments: 0

New technical papers recently added to Semiconductor Engineering’s library: [table id=519 /] Find more semiconductor research papers here. » read more

A Manufacturing Approach That Brings Diamond Quantum Photonics Closer To Industrial Production (MIT, KAUST et al.)
By Technical Paper Link - 02 Feb, 2026 - Comments: 0

"Foundry-Enabled Patterning of Diamond Quantum Microchiplets for Scalable Quantum Photonics" was published by researchers at MIT, KAUST, PhotonFoundries and MITRE. Abstract "Quantum technologies promise secure communication networks and powerful new forms of information processing, but building these systems at scale remains a major challenge. Diamond is an especially attractive material fo... » read more

ML for Energy-Performance-Aware Scheduling On Heterogeneous Multicore Architectures (Cambridge)
By Technical Paper Link - 02 Feb, 2026 - Comments: 0

University of Cambridge researchers published "Machine Learning for Energy-Performance-aware Scheduling." Abstract "In the post-Dennard era, optimizing embedded systems requires navigating complex trade-offs between energy efficiency and latency. Traditional heuristic tuning is often inefficient in such high-dimensional, non-smooth landscapes. In this work, we propose a Bayesian Optimizatio... » read more

HW-Triggered Backdoors Across Common GPU Accelerators (BIFOLD, TU Berlin, CISPA)
By Technical Paper Link - 02 Feb, 2026 - Comments: 0

A new technical paper titled "Hardware-Triggered Backdoors" was published by researchers at Berlin Institute for the Foundations of Learning and Data (BIFOLD), TU Berlin and CISPA Helmholtz Center for Information Security. Abstract "Machine learning models are routinely deployed on a wide range of computing hardware. Although such hardware is typically expected to produce identical result... » read more

Chiplet Fundamentals For Engineers: eBook
By Bryon Moyer - 02 Feb, 2026 - Comments: 1

Multi-die assemblies are the next phase of Moore's Law, scaling up and out  to improve performance and add flexibility into designs. By decomposing SoCs into building blocks, yield improves for the individual dies and overall performance increases because a chip is no longer bound by reticle limits. But this is much harder than it sounds. Chiplets don't just snap together like LEGOs, and so... » read more

The Verification Conundrum
By Brian Bailey - 02 Feb, 2026 - Comments: 2

When constrained random test pattern generation became the de facto way to verify designs, reference models became necessary to check that a design was producing the correct output. These were often distributed across several models, such as checkers, scoreboards and assertions. Another model that had to be created was the coverage model. It was required because you had to know if a generate... » read more

Solving Real-World AI Bottlenecks
By André Bonnardot - 02 Feb, 2026 - Comments: 0

The race to build smarter and faster AI chips continues to surge. This is especially true in autonomous vehicles that interpret the world in milliseconds, edge accelerators that push trillions of operations per second, hyperscale data-center processors that drive massive workloads, and next-generation consumer devices that demand ever-higher intelligence. As modern system-on-chip (SoC) architec... » read more

Benchmark For AI-Aided Chip Design That Evaluates LLMs Across 3 Critical Tasks (UCSD, Columbia)
By Technical Paper Link - 30 Jan, 2026 - Comments: 0

Researchers at UCSD and Columbia University published "ChipBench: A Next-Step Benchmark for Evaluating LLM Performance in AI-Aided Chip Design." Abstract "While Large Language Models (LLMs) show significant potential in hardware engineering, current benchmarks suffer from saturation and limited task diversity, failing to reflect LLMs' performance in real industrial workflows. To address t... » read more

Chip Industry Week In Review
By The SE Staff - 30 Jan, 2026 - Comments: 0

Big deals and fundings Teradyne and MultiLane are forming a joint venture, MultiLane Test Products (MLTP), to accelerate the development of test solutions for high speed data connections.  Teradyne will be the majority owner. Ricursive Intelligence raised $300M Series A for AI-driven IC design. IonQ plans to acquire SkyWater for ~$1.8B, creating a "vertically integrated full-stack q... » read more

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