Advanced High Throughput e-Beam Inspection With DirectScan


Optical inspection cannot resolve critical defects at advanced nodes and cannot detect subsurface defects. Especially at 7nm and below, many yield and reliability killer defects are the result of interactions between lithography, etch, and fill. These defects often will have part per billion (PPB) level fail rates. Conventional eBeam tools lack the throughput to measure PPB level fail rates. A ... » read more

Assuring Reliable Processor Performance At Scale


In today’s data center environment, resilience is key. Cloud providers are built on as-a-service business models, where uptime is critical to ensure their customers’ business continuity. Reputation and competitiveness require service at extremely high performance, low power, and increasing functionality, with zero tolerance for unplanned downtime or errors. If you’re a hyperscaler, o... » read more

Next-Gen Transistors


Nanosheets, or more generally, gate-all-around FETs, mark the next big shift in transistor structures at the most advanced nodes. David Fried, vice president of computational products at Lam Research, talks with Semiconductor Engineering about the advantages of using these new transistor types, along with myriad challenges at future nodes, particularly in the area of metrology. » read more

Startup Funding: February 2022


Mega-rounds dominated venture funding in February, with ten companies seeing investment of $100 million or more, five of which exceeded $200 million. Automotive was the big winner, with seven of the ten companies involved in either developing ADAS and autonomous driving, building electric vehicles, or making components to go in cars. The largest round of the month falls into that last category,... » read more

Research Bits: March 7


Optical signal processing with acoustic waves Researchers from Pohang University of Science & Technology (POSTECH) demonstrated an optical-wave signal that can be amplified or canceled using optically driven acoustic waves on a silicon chip. Optical signal processing using Brillouin scattering, in which acoustic waves scatter light, has been demonstrated in nanophotonic structures. But ... » read more

Week In Review: Manufacturing, Test


Packaging ASE, AMD, Arm, Google, Intel, Meta, Microsoft, Qualcomm, Samsung, and TSMC have announced the formation of a consortium that will establish a die-to-die interconnect standard and foster an open chiplet ecosystem. The founding companies also ratified the UCIe specification, an open industry standard developed to establish a standard interconnect at the package level. The UCIe 1.0 s... » read more

Week In Review: Design, Low Power


Tools & IP Imperas Software introduced the RISC-V Verification Interface (RVVI). The open standard and methodology can be adapted to any configuration permitted within the RISC-V specifications. RVVI defines interfaces between RTL, reference model, and testbench for RISC-V design verification, with the aim of making RISC-V processor DV reusable. It supports multi-hart, superscalar, and out... » read more

Week In Review: Auto, Security, Pervasive Computing


From pandemic to war — some of the news this week highlights reactions to Russia’s invasion of Ukraine. Pervasive computing, IoT, 5G and beyond SpaceX sent Starlink satellite dishes to Ukraine to enable Ukrainian access to the Internet. The caveat is the uplink signals from satellite equipment can be used to triangulate the position of the dish, which can then be hit by missile. The dis... » read more

Where Do Memory Maps Come From?


A memory map is the bridge between a system-on-chip (SoC) and the firmware and software that is executed on it. Engineers may assume the map automatically appears, but the reality is much more involved. The union of hardware (HW) and software (SW) demands both planning and compromise. The outcome of this merger will not be fully realized until the magical day when the system comes to life. T... » read more

Verifying Side-Channel Security Pre-Silicon


As security grows in importance, side-channel attacks pose a unique challenge because they rely on physical phenomena that aren’t always modeled for the design verification process. While everything can be hacked, the goal is to make it so difficult that an attacker concludes it isn't worth the effort. For side-channel attacks, the pre-silicon design is the best place to address any known ... » read more

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