Silicon-based Power Semis Face Challenges
By Mark LaPedus - 17 Feb, 2022 - Comments: 0

Suppliers of power semiconductors continue to develop and ship devices based on traditional silicon technology, but silicon is nearing its limits and faces increased competition from technologies like GaN and SiC. In response, the industry is finding ways to extend traditional silicon-based power devices. Chipmakers are eking out more performance and prolonging the technology, at least in th... » read more

The Right Project Is Key For Photomask Adoption Of Deep Learning
By Jan Willis - 17 Feb, 2022 - Comments: 0

Deep learning (DL) has become an integral part of the success of many companies. There have been many papers and some reported successes in semiconductor manufacturing, yet only 22% of the luminaries participating in the 2021 eBeam Initiative Luminaries survey see DL as a competitive advantage for photomask making by next year, as shown in figure 1. Looking at that chart, the luminaries believe... » read more

Warpage Of Compression Molded SiP Strips
By JCET - 17 Feb, 2022 - Comments: 0

By Eric Ouyang, Yonghyuk Jeong, JaeMyong Kim, JaePil Kim, OhYoung Kwon, and Michael Liu of JCET; and Susan Lin, Jenn An Wang, Anthony Yang, and Eric Yang of CoreTech System (Moldex3D). Abstract System-in-Package (SiP) technology has been used for a wide range of electronic devices, but the warpage behavior of the package can be difficult to control and predict due to complex manufacturing p... » read more

Chip-Last HDFO (High-Density Fan-Out) Interposer-PoP
By Amkor - 17 Feb, 2022 - Comments: 0

Interposer Package-on-Package (PoP) technology was developed and has been in very high-volume production over the last several years for high-end mobile application processors (APs). This is due to its advantages of good package design flexibility, controllable package warpage at room temperature (25°C) and high temperature (260°C), reduced assembly manufacturing cycle time and chip-last asse... » read more

3D-IC: Great Opportunities, Great Challenges
By John Lee - 17 Feb, 2022 - Comments: 0

The growing adoption of 2.5D and 3D integrated circuits (3D-ICs) marks a major inflection point in the world of semiconductor design. Electronic designers demand greater integration densities and faster data transfer rates to meet the growing performance requirements of AI/ML, 5G/6G networks and autonomous vehicles as these technologies have outpaced the capabilities of any single chip. 3D-IC t... » read more

Precision Selective Etch Tools Pave The Way For The Next Technology Inflection
By Tim Archer - 17 Feb, 2022 - Comments: 0

Over the past decade, the need for increasingly smaller, denser, more powerful chips has been driving semiconductor manufacturers to move away from planar structures in favor of increasingly complex three-dimensional (3D) structures. Why? Simply put, stacking elements vertically enables greater density. Use of 3D architectures to support advanced logic and memory applications represents the ... » read more

Unsolved Issues In Next-Gen Photomasks
By Mark LaPedus - 17 Feb, 2022 - Comments: 0

Experts at the Table: Semiconductor Engineering sat down to discuss optical and EUV photomasks issues, as well as the challenges facing the mask business, with Naoya Hayashi, research fellow at DNP; Peter Buck, director of MPC & mask defect management at Siemens Digital Industries Software; Bryan Kasprowicz, senior director of technical strategy at Hoya; and Aki Fujimura, CEO of D2S. What f... » read more

A Sub-1 Hz Resonance Frequency Resonator Enabled By Multi-Step Tuning For Micro-Seismometer
By Coventor - 17 Feb, 2022 - Comments: 0

We propose a sub-1 Hz resonance frequency MEMS resonator that can be used for seismometers. The low resonance frequency is achieved by an electrically tunable spring with an ultra-small spring constant. Generally, it is difficult to electrically fine-tune the resonance frequency at a near-zero spring constant because the frequency shift per voltage will diverge at the limit of zero spring const... » read more

Preparing For 3D-ICs
By Ed Sperling - 16 Feb, 2022 - Comments: 1

Experts at the Table: Semiconductor Engineering sat down to discuss the changes in design tools and methodologies needed for 3D-ICs, with Sooyong Kim, director and product specialist for 3D-IC at Ansys; Kenneth Larsen, product marketing director at Synopsys; Tony Mastroianni, advanced packaging solutions director at Siemens EDA; and Vinay Patwardhan, product management group director at Cadence... » read more

Blog Review: Feb. 16
By Jesse Allen - 16 Feb, 2022 - Comments: 0

Arm's Mark Nicholson explains the software side of the Morello project to implement a prototype security-focused architecture, presenting a high-level view of the software stacks and discussing the status and roadmap of a range of activities. Synopsys' Ron Lowman finds that as IoT technology and capabilities of portable devices expand, the deployment of 5G networks and interest in AI and aut... » read more

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