Chip Industry’s Technical Paper Roundup: Jan. 31


New technical papers added to Semiconductor Engineering’s library. [table id=77 /] If you have research papers you are trying to promote, we will review them to see if they are a good fit for our global audience. At a minimum, papers need to be well researched and documented, relevant to the semiconductor ecosystem, and free of marketing bias. There is no cost involved for us posting l... » read more

Research Bits: Jan. 31


The power of proximity Researchers from Department of Energy’s Lawrence Berkeley National Laboratory (Berkeley Lab), Stanford, and University of California Berkeley have observed that electrons transfer heat rapidly between layers of the 2D semiconductor materials tungsten diselenide (WSe2) and tungsten disulfide (WS2). The electrons acted as a bridge between the two materials, the layers of... » read more

Chip Industry’s Startup Funding 2022: Sortable Funding Chart


Below is a sortable chart that accompanies your e-book purchase of Semiconductor Engineering’s 2022 Startup Funding report. Simply click on the top headers to determine your primary sort. This content is copyrighted by Sperling Media Group LLC. [table id=startup-fund-2022FY /] This content is copyrighted by Sperling Media Group LLC. » read more

Importance Of Qualifying IP Revisions


Design intellectual property (IP) is the fundamental building block of the modern system on chip (SoC). As the scale and complexity of SoCs increases, usage of design IP blocks also increases rapidly, as they enable modularization and re-use of design components. As a result, the usage of design IP has grown rapidly in the past decade. An IP data library consists of many views and formats, w... » read more

Scan Pattern Portability From PSV To ATE To SLT To IST


By Ash Patel and Karthik Natarajan Chip testing has become increasingly complex due to the number of variables impacting designs – from design size and complexity, to high transistor counts on advanced technology nodes, to 2.5D/3D packaging, to manufacturing variability. All of these combine to make testing today's chips and packages more complicated than ever before. The number of test pa... » read more

Improving Performance And Power With HBM3


HBM3 swings open the door to significantly faster data movement between memory and processors, reducing the power it takes to send and receive signals and boosting the performance of systems where high data throughput is required. But using this memory is expensive and complicated, and that likely will continue to be the case in the short term. High Bandwidth Memory 3 (HBM3) is the most rece... » read more

Wafer Scale Transfer of 2D Materials, Graphene


A new technical paper titled "Assessment of Wafer-Level Transfer Techniques of Graphene with Respect to Semiconductor Industry Requirements" was published by researchers at Infineon Technologies AG, RWTH Aachen University, Protemics, and Advantest. Abstract "Graphene is a promising candidate for future electronic applications. Manufacturing graphene-based electronic devices typically requ... » read more

Side-Channel Attacks Via Cache On the RISC-V Processor Configuration


A technical paper titled "A cross-process Spectre attack via cache on RISC-V processor with trusted execution environment" was published by researchers at University of Electro-Communication, Academy of Cryptography Techniques, Technology Research Association of Secure IoT Edge Application based on RISC-V Open Architecture (TRASIO), and AIST. "This work proposed a cross-process exploitation ... » read more

Heterogeneous Multi-Core HW Architectures With Fine-Grained Scheduling of Layer-Fused DNNs


A technical paper titled "Towards Heterogeneous Multi-core Accelerators Exploiting Fine-grained Scheduling of Layer-Fused Deep Neural Networks" was published by researchers at KU Leuven and TU Munich. Abstract "To keep up with the ever-growing performance demand of neural networks, specialized hardware (HW) accelerators are shifting towards multi-core and chiplet architectures. So far, thes... » read more

Mitigating Silent Data Corruptions in High Performance Computing


A new technical paper titled "Mitigating silent data corruptions in HPC applications across multiple program inputs" was published by researchers at University of Iowa, Baidu Security, and Argonne National Lab. The paper was a Best Paper finalist at SC22. The researchers "propose MinpSID, an automated SID framework that automatically identifies and re-prioritizes incubative instructions in a... » read more

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