Reducing Design Margins With Silicon Model Calibration
By Guy Cortez - 09 Jul, 2024 - Comments: 0

By Guy Cortez and Mark Laird It’s no secret to anyone that chip design gets harder every year. There are two major trends driving these ever-increasing challenges. The first is the continual scaling down to smaller design nodes. Although the pace of new node introduction has slowed somewhat in recent years, the impact of each new geometry and process is more dramatic than ever before. Acce... » read more

Effective Monitoring, Test, and Repair of Multi-Die Designs
By Synopsys - 09 Jul, 2024 - Comments: 0

Despite clear advantages, there are numerous new challenges that need to be addressed for successful multi-die realization. The multi-die test challenges include: Bare chiplet level (pre-bond) Probe, dedicated/functional pads for test Test, diagnosis, and repair Interconnects (mid/post-bond) Die-to-die test access Lane test, diagnosis, and repair Multi-die ... » read more

Delivering On Power During HPC Test
By Anne Meixner - 09 Jul, 2024 - Comments: 0

The industry’s insatiable need for power in high-performance computing (HPC) is creating problems for test cells, which need to deliver very high currents at very consistent voltage levels through the power delivery network (PDN). In response, ATE, wafer probe, and contactor vendors are introducing some innovative approaches and test procedures that can ensure robust power delivery to ATE pro... » read more

Digital Twins Find Their Footing In IC Manufacturing
By Laura Peters - 09 Jul, 2024 - Comments: 0

Momentum is building for digital twins in semiconductor manufacturing, tying together the various processes and steps to improve efficiency and quality, and to enable more flexibility in the fab and assembly house. The movement toward digital twins opens up a slew of opportunities, from building and equipping new fabs faster to speeding yield ramps by reducing the number of silicon-based tes... » read more

X-ray Inspection Becoming Essential In Advanced Packaging
By Gregory Haley - 09 Jul, 2024 - Comments: 0

X-ray technology is moving into the mainstream of chip manufacturing as complex assemblies and advanced packaging make it increasingly difficult to ensure these devices will work as expected throughout their lifecycles. A single defect in a chiplet or interconnect can transform a complex advanced package into expensive scrap, and the risk only increases as the chip industry shifts from homog... » read more

Testing PAs under Digital Predistortion and Dynamic Power Supply Conditions
By NI - 09 Jul, 2024 - Comments: 0

The power amplifier (PA) – as either a discrete component or part of an integrated front end module (FEM) – is one of the most integral RF integrated circuits (RFICs) in the modern radio. In this application note, you will learn different techniques for testing PAs through an interactive application note with multiple how-to videos. To address these linearity and efficiency requirements,... » read more

Automotive Semiconductors Require Integrated Test Solution
By Toni Dircherl - 09 Jul, 2024 - Comments: 0

The automotive semiconductor test market is experiencing organic growth as chipmakers produce higher volumes of devices serving an array of automotive applications. In addition, the range of applications for automotive-grade semiconductors is evolving as the technology advances. Manufacturers of automated test equipment (ATE) are adapting to ensure their systems can handle devices ranging from ... » read more

Leveraging Machine Learning in Semiconductor Yield Analysis
By DR Yield - 09 Jul, 2024 - Comments: 0

Searching through wafer maps looking for spatial patterns is not only a very time-consuming task to be done manually, it’s also prone to human oversight and error, and nearly impossible in a large fab where there are thousands of wafers a day being processed. We developed a tool that applies automatic spatial pattern detection algorithms using ML, parametrizing pattern recognition and clas... » read more

Real-Time Safety Monitoring for Predictive and Prescriptive Maintenance in Advanced Automotive Electronics
By proteanTecs - 09 Jul, 2024 - Comments: 0

Software Defined, Electric, and Autonomous vehicles are driving new roadmaps for advanced electronics. Centralized architectures have introduced cutting-edge ECUs and SOCs. Coupled with stringent standardization, automotive manufacturers and OEMs are tasked with achieving functional safety in an ever-developing landscape. Maintaining safety standards without compromising performance and cos... » read more

RTL Optimization Via Verified E-Graph Rewriting (Intel, Imperial College London)
By Technical Paper Link - 08 Jul, 2024 - Comments: 0

A technical paper titled “ROVER: RTL Optimization via Verified E-Graph Rewriting” was published by researchers at Intel Corporation and Imperial College London. Abstract: "Manual RTL design and optimization remains prevalent across the semiconductor industry because commercial logic and high-level synthesis tools are unable to match human designs. Our experience in industrial datapath des... » read more

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