Improving GaN Device Architectures
By Katherine Derbyshire - 23 Jan, 2025 - Comments: 0

As the universe of applications for power devices grows, designers are finding that no single semiconductor can cover the full range of voltage and current requirements. Instead, combination circuits use different materials for different parts of the overall operating range. GaN is especially well-established in low-power applications like chargers for personal electronics, while silicon and... » read more

New Class Of Memory: Managed-Retention Memory or MRM (Microsoft Research)
By Technical Paper Link - 22 Jan, 2025 - Comments: 0

A new technical paper titled "Managed-Retention Memory: A New Class of Memory for the AI Era" was published by researchers at Microsoft. Abstract "AI clusters today are one of the major uses of High Bandwidth Memory (HBM). However, HBM is suboptimal for AI workloads for several reasons. Analysis shows HBM is overprovisioned on write performance, but underprovisioned on density and read band... » read more

Livelocks And Deadlocks In NoCs
By Ed Sperling - 22 Jan, 2025 - Comments: 0

Devices that are stuck in a specific state, or which appear to be making progress even though they are not, are common problems in complex systems. Processing elements need to fetch data they don't have from routers may be frozen out by other processors, a problem that is exacerbated by common bus protocols. Ashish Darbari, CEO of Axiomise, talks about how to identify potential bottlenecks, why... » read more

Automotive OEMs Face Multiple Technology Adoption Challenges
By Ann Mutschler - 22 Jan, 2025 - Comments: 0

Experts At The Table: The automotive ecosystem is in the midst of significant change. OEMs and tiered providers are grappling with how to deal with legacy technology while incorporating ever-increasing levels of autonomy, electrification, and software-defined vehicle concepts, just to name a few. Semiconductor Engineering sat down to discuss these and other related issues with Wayne Lyons, seni... » read more

Blog Review: Jan. 22
By Jesse Allen - 22 Jan, 2025 - Comments: 0

Cadence's David Shin provides an overview of the eUSB2V2 specification, which scales up to 4.8Gbps of data rate and provides the flexibility to configure either asymmetrical or symmetrical links depending on the intended application. Siemens EDA's Spencer Acain highlights the key role of AI in semiconductor testing, including the addition of analytical AI in DFT tools and how applying machin... » read more

Parallelized Compilation Pipeline Optimized for Chiplet-Based Quantum Computers
By Technical Paper Link - 21 Jan, 2025 - Comments: 0

A new technical paper titled "Modular Compilation for Quantum Chiplet Architectures" was published by researchers at Northwestern University. Abstract "As quantum computing technology continues to mature, industry is adopting modular quantum architectures to keep quantum scaling on the projected path and meet performance targets. However, the complexity of chiplet-based quantum devices, cou... » read more

Global IC Fabs And Facilities Report: 2024
By Liz Allan - 21 Jan, 2025 - Comments: 0

The chip industry made significant capital investments this year to build new fabs and facilities or expand existing premises. A number of sites were dedicated to SiC, GaN, DRAM, HBM, along with packaging and assembly by OSATs, and essential gases, chemicals, and other components. More than a dozen R&D centers were also established for 8-inch wafers, EUV, and advanced packaging. Investments... » read more

3D Integration And Test Results From TSV-Processed Chips (CERN et al.)
By Technical Paper Link - 20 Jan, 2025 - Comments: 0

A new technical paper titled "3D integration of pixel readout chips using Through-Silicon-Vias" was published by researchers at CERN, IZM Fraunhofer and University of Geneva. Abstract "Particle tracking and imaging detectors are becoming increasingly complex, driven by demands for densely integrated functionality and maximal sensitive area. These challenging requirements can be met using 3D... » read more

Impact of Extremely Low Temperatures On The 5nm SRAM Array Size and Performance
By Technical Paper Link - 20 Jan, 2025 - Comments: 0

A new technical paper titled "Novel Trade-offs in 5 nm FinFET SRAM Arrays at Extremely Low Temperatures" was published by researchers at University of Stuttgart, IIT Kanpur, National Yang Ming Chiao Tung University, Khalifa University, and TU Munich. Abstract "Complementary metal–oxide–semiconductor (CMOS)-based computing promises drastic improvement in performance at extremely low temp... » read more

Liquid-Infused Nanostructured Composites As A Universal Thermal Interface Solution for Cooling Applications
By Technical Paper Link - 20 Jan, 2025 - Comments: 0

A new technical paper titled "Liquid-infused nanostructured composite as a high-performance thermal interface material for effective cooling" was published by researchers at Carnegie Mellon University, Oregon State University and Arieca. Abstract "Effective heat dissipation remains a grand challenge for energy-dense devices and systems. As heterogeneous integration becomes increasingly inev... » read more

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