The challenges of manual NoC implementation and how smart automation improves NoC performance.
Today’s high-end SoCs contain many heterogeneous processing elements to address the needs of HPC and AI applications. These include Central Processing Units (CPUs), Graphics Processing Units (GPUs), Neural Processing Units (NPUs), Tensor Processing Units (TPUs), and other hardware accelerators. Furthermore, IPs may contain clusters of these processor cores, and SoC subsystems may include arrays of these clusters.
SoCs of this caliber face significant design challenges related to performance, power efficiency, and time-to-market pressures. Although there has grown to be some level of automation, networks-on-chip (NoCs) have primarily been implemented by hand. A lack of NoC expertise in many development teams has compounded existing design challenges. Today, every complex SoC uses a NoC-based interconnect. The number of NoCs on modern SoCs typically ranges between 5 and 20 or more, where each may employ a different topology. The increased capability and complexity of today’s high-end SoC designs mean they surpass the human ability to create NoCs without smart assistance.
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