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Power Aware Intent And Structural Verification Of Low-Power Designs
By Progyna Khondkar - 08 Mar, 2018 - Comments: 3

Power aware static verification, more popularly known as PA-Static checks, is performed on designs that adopt certain power dissipation reduction techniques through the power intent or [gettech id="31044" t_name="UPF"]. The term static originates from verification tools and methodologies that applies a set of pre-defined power aware (PA) or multi-voltage (MV) rules based on the power requiremen... » read more

How Robust Is Your ESD Protection? Are You Sure?
By Derong Yan - 08 Feb, 2018 - Comments: 0

Electrostatic discharge (ESD) protection is critical at advanced nodes to safeguard designs against effects intensified by shrinking transistor dimensions and oxide layer thicknesses. On the other hand, ESD protection checks are consuming vastly more runtime and memory due to the growing die sizes of system-on-chips (SoCs) and the number of transistors they can hold. Designers are facing increa... » read more

A Simple Way To Improve Automotive In-System Test
By Jeff Mayer - 11 Jan, 2018 - Comments: 0

The remarkable growth in automotive IC design has prompted a focus on ISO26262 functional safety compliance, which includes both high-quality manufacturing test and a minimum stuck-at test coverage of 90% for in-system test. Designers must also control IC test data volumes, test application times, and test costs. A new test point technology that improves in-system test coverage and reduces patt... » read more

Co-Modeling Takes Emulation To The Next Level: System-Of-Systems
By Ron Squiers - 14 Dec, 2017 - Comments: 0

As designs move beyond System-on-Chip (SoC) to more complex System-of-Systems (SoS), it’s essential for design teams to effectively verify that these systems function together as intended. Increasingly, system design companies are turning to emulators as the only verification platform with the capacity and performance to validate that their SoC and SoS designs function as intended. Today�... » read more

An Incremental Approach To Reusing Automated Tests From IPs To SoCs
By Matthew Ballance - 09 Nov, 2017 - Comments: 0

Over the past few years, lots of energy has been invested in improving the productivity and quality-of-results of design verification. A promising effort toward this end is that both commercial and in-house tools have been developed to improve the productivity and efficiency of verification at the block, subsystem, and system levels. These tools raise the level of abstraction, increase test-gen... » read more

Body Bias: What It Is, And Why You Should Care
By Flint Yoder - 12 Oct, 2017 - Comments: 1

In case you hadn’t noticed, the use of integrated circuits (ICs) has exploded over the past decade. From the cheapest novelty toy to automobiles to implanted medical devices, it seems like everything we touch has an electronic component in it somewhere. Not surprisingly, that growth has brought with it a vastly expanded number and variety of IC design requirements that design companies must s... » read more

How Virtual Emulation Gives The Storage Market A Leg Up
By Ben Whitehead - 14 Sep, 2017 - Comments: 0

By Ben Whitehead and Paul Morrison The storage market demands that huge amounts of data and information be stored securely and be accessible anywhere and anytime, driving the adoption of key technologies and use models. According to GSMAintelligence.com, newly created digital data is doubling every two years. This means increasing amounts of storage must be available at the same pace. A... » read more

UPF Power Domains And Boundaries
By Progyna Khondkar - 10 Aug, 2017 - Comments: 0

The Universal Power Format (UPF) plays a central role in mitigating dynamic and static power in the battle for low-power in advanced process technology. A higher process node is definitely attractive as more functionality integration is possible in a smaller die area at a lower cost. However, in reality, this comes at the cost of exponentially increasing leakage power. This is because the minim... » read more

Estimating Power And Performing Optimization
By Guillaume Boillet - 13 Jul, 2017 - Comments: 0

Power analysis and optimization have gained importance over the last few years. During this time it has become obvious how critical it is to use realistic payloads to accurately estimate power and perform optimization tasks. Designers have a range of different objectives and concerns when it comes to power. On one side, a team wants to ensure that the average power of their chip is low enough t... » read more

Libraries: Standardization and Requirements For Power-Aware Dynamic Simulation
By Progyna Khondkar - 08 Jun, 2017 - Comments: 0

INTRODUCTION Multivoltage (MV) based power-aware (PA) design verification and implementation methodologies requires special power management attributes in libraries for standard, MV and Macro cells for two distinctive reason. The first aspect is to provide power and ground (also bias) supply or PG-pin information, which is mandatory for PA verification. The second reason is to provide a distin... » read more

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