category: IP And LP In SoCs

category: IoT, Security & Automotive

The Power-Performance Paradox
By Mike Thompson - 13 Mar, 2014 - Comments: 0

The Changing World Technology is shaping and altering the world around us. Reality is being augmented and “virtual reality” is becoming the norm. Video is becoming more immersive, offering 3D effects and 4K resolution, with 8K on the horizon. Cars are a technology showcase that in a few years conceivably will take over the driving for us. Our ability to interact with technology through tou... » read more

It’s Never Too Early
By David Hsu - 13 Feb, 2014 - Comments: 0

My previous postings discussed the importance of native low-power capabilities and coverage in simulation flows. The complement to this is incorporating complete and thorough low power checking throughout the design and implementation flow, and find and fix as many low-power bugs as possible before simulation. With the right checking tools and proper deployment, doing so enables the possibility... » read more

Using USB 3.1’s Multiple INs To Reach 10 Gbps Data Rates
By Matthew Myers - 16 Jan, 2014 - Comments: 0

In January 2013, the USB-IF announced USB 3.1, a new generation of the protocol that will double USB 3.0 data throughput performance to 10 Gbps. In addition to this increased speed, the specification requires compatibility with existing cables, connectors, software stacks, and device class protocols. USB 3.1 products must support existing 5 Gbps and new 10 Gbps hubs and devices, as well as olde... » read more

Coverage-Driven Verification Isn’t Complete Without Low-Power Metrics
By David Hsu - 05 Dec, 2013 - Comments: 0

Coverage-driven verification enables the structured, measurable and manageable verification of today’s extraordinarily large and complex SoCs. Establishing predetermined objectives and planning for verification tasks is crucial to achieving closure on overall goals, and creating the comprehensive set of metrics to track during the verification process enables schedule predictability and confi... » read more

FinFET Impacts For Reducing Physical IP Power Consumption
By Navraj Nandra - 07 Nov, 2013 - Comments: 0

FinFET devices were developed to address the need for improved gate control to suppress leakage current (IOFF); DIBL (drain-induced barrier lowering); and process‐induced variability below 32-nanometer. FinFET technology is now in volume production. To fully realize the advantages of FinFET devices, physical IP must follow the same trajectory that has benefited digital design. That include... » read more

Low Power Verification – “X” Marks the Spot
By David Hsu - 10 Oct, 2013 - Comments: 1

Welcome to a new discussion on a range of topics we think will be interesting to folks who design and verify SoCs. Though the name of this blog denotes two top attributes of SoCs—IP implementation and the pervasive need for low power (LP), we certainly may go far beyond the scope of these topics in upcoming posts. We’ll start with a topic on the LP side, and going forward we’ll alternate ... » read more

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