Advanced Design Debug Demands Integrated Verification Management


Design verification has been the dominant portion of chip development for years, and the challenges grow bigger every day. Single dies continue to grow in transistor count and complexity. Advanced techniques such as 2.5D and 3D multi-die systems and emerging technologies such as wafer-scale integration pack even more transistors and functionality into a single device. This situation has created... » read more

Latency Considerations For 1.6T Ethernet Designs


Since its 1980s debut with 10Mbps shared LANs over coaxial cables, Ethernet has seen consistent advancements, now with the potential to support speeds up to 1.6Tbps. This progression has allowed Ethernet to serve a wider range of applications, such as live streaming, Radio Access Networks and industrial control, emphasizing the importance of reliable packet transfer and quality of service. With... » read more

Using Virtual Metal Fill To Predict The Impact Of High Level Nets


A recent blog post discussed the use of virtual metal fill (VMF) to predict the effects of real metal fill when performing RC extraction on a chip layout. This enables static timing analysis (STA) closely correlated with final post-fill results without incurring the time to perform the actual metal fill insertion during the layout-STA loop. VMF is fast enough to be run in every iteration of thi... » read more

Developing Energy-Efficient AI Accelerators For Intelligent Edge Computing And Data Centers


Artificial intelligence (AI) accelerators are deployed in data centers and at the edge to overcome conventional von Neumann bottlenecks by rapidly processing petabytes of information. Even as Moore’s law slows, AI accelerators continue to efficiently enable key applications that many of us increasingly rely on, from ChatGPT and advanced driver assistance systems (ADAS) to smart edge device... » read more

Evolution Of Equalization Techniques In High-Speed SerDes For Extended Reaches


The relentless demand for massive amounts of data is accelerating the pace of high-performance computing (HPC) within the high-speed Ethernet realm. This escalation, in turn, intensified the complexity associated with designing networking SoCs, including switches, NICs, retimers, and pluggable modules. Such growth is accelerating the demand for bandwidth hungry applications to transition from 4... » read more

Using Virtual Metal Fill To Solve Real Design Problems


People learning about semiconductor manufacturing might well be confused by the concept of metal fill. It seems perfectly intuitive that laying out a complex chip will result in some regions with fewer transistors and metal interconnect than others. It makes sense that there will be areas that are mostly empty. So why spend money on more complicated masks and on extra metal just to fill those e... » read more

From Known Good Die To Known Good System With UCIe IP


Multi-die systems are made up of several specialized functional dies (or chiplets) that are assembled in the same package to create the complete system. Multi-die systems have recently emerged as a solution to overcome the slowing down of Moore’s law by providing a path to scaling functionality in the packaged chip in a way that is manufacturable with good yield. Additionally, multi-die sy... » read more

How eMRAM Addresses The Power Dilemma In Advanced-Node SoCs


By Rahul Thukral and Bhavana Chaurasia Our intelligent, interconnected, data-driven world demands more computation and capacity. Consider the variety of smart applications we now have. Cars can transport passengers to their destinations using local and remote AI decision-making. Robot vacuum cleaners keep our homes tidy, and smartwatches can detect a fall and call emergency services. With hi... » read more

100G Ethernet IP For Edge Computing


The presence of Ethernet in our lives has paved the way for the emergence of the Internet of Things (IoT). Ethernet has connected everything around us and beyond, from smart homes and businesses, to industries, schools, and governments. This specification is even found in our vehicles, facilitating communication between internal devices. Ethernet has enabled high-performance computing data cent... » read more

How To Raise Reliability, Availability, And Serviceability Levels For HPC SoCs


By Charlie Matar, Rita Horner, and Pawini Mahajan While once the domain of large data centers and supercomputers, high-performance computing (HPC) has become rather ubiquitous and, in some cases, essential in our everyday lives. Because of this, reliability, availability, and serviceability, or RAS, is a concept that more HPC SoC designers should familiarize themselves with. RAS may sound... » read more

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