What Is UCIe?


The semiconductor industry is undertaking a major strategy shift towards multi-die systems. The shift is fueled by several converging trends: Size of monolithic SoCs is becoming too big for manufacturability Some SoC functionalities may require different process nodes for optimal implementation Desire for enhanced product scalability and composability is increasing Multi-die syste... » read more

Signoff-Accurate Partial Layout Extraction And Early Simulation


It is a rewarding experience for EDA developers and users to collaborate on deploying advanced techniques to improve design productivity. This blog will describe the experience of collaborating with customers on a new technology for reducing the number of analog design iterations. Analog design requires that engineers balance the needs to 1) reach market quickly 2) deliver high quality 3) at lo... » read more

PCIe 6.0, NVMe, And Emerging Form Factors For Storage Applications


PCIe 6.0 implementations are expandable and hierarchical with embedded switches or switch chips, allowing one root port to interface with multiple endpoints (such as storage devices, Ethernet cards, and display drivers). While the introduction of PCIe 6.0 at 64GT/s helped to increase the bandwidth available for storage applications with minimal or no increase in latency, the lack of coherency s... » read more

Bringing RFIC Design And Verification Into The Modern Era


For decades, developers of radio frequency (RF) chips and other analog/mixed-signal (AMS) integrated circuits (ICs) have used traditional techniques for design and verification. Most RFIC designers have continued to hand-craft active and passive devices, manually place and route their circuits, and rely on the bring-up lab to validate their pre-silicon SPICE simulations. It is often said that a... » read more

Meeting 112 SerDes Based System Design Challenges


The need for higher bandwidth networking equipment as well as connectivity in the cloud and hyperscale data centers is driving the switch technology transition from 25Tb/s (terabytes) to 51Tb/s and soon to 100Tb/s. The industry has chosen Ethernet to drive the switch market, using 112G SerDes or PHY technology today and 224G SerDes in the future. This article describes how designers can overcom... » read more

If These Chips Could Talk: Actionable Insights From Path Margin Monitors


One of the most important current trends in electronics is the gathering and analysis of big data to reap benefits in cost, power, performance, and reliability. This is becoming common in the chip development flow. For example, data harvested from simulation regressions can aid in debug and reaching coverage goals. Machine learning (ML) uses the results of many passes through implementation (lo... » read more

Accelerating Circuit Simulation 10x With GPUs


By Samad Parekh (Synopsys) and Srinivas Kodiyalam (NVIDIA) Many aspects of semiconductor design and verification have an ever-growing “need for speed” that has outpaced the performance improvements available by running on CPUs. Electronic design automation (EDA) companies have responded by creating smarter software algorithms to improve simulation time, sometimes at the expense of relaxe... » read more

AI Everywhere: Accelerating Chip Design At Every Node


Over the last few years, artificial Intelligence (AI) has increasingly played a significant role in the chip development process. But, when people talk about AI-designed chips, it is usually in the context of the latest, cutting-edge designs manufactured at advanced process nodes (7/5nm and smaller) and for good reason. Such designs constantly push the bounds of power, performance, and area (PP... » read more

The Ethernet Standard: To IP And Beyond


Ethernet is ubiquitous—it is the core technology that defines the Internet and serves to connect the world in ways that people could not imagine even one generation ago. HPC clusters are working on solving the most challenging problems facing humanity—and cloud computing is the service hosting many of the application workloads struggling with these questions. While alternative network infra... » read more

Run Realistic Software For Full Chip Power Signoff


In the real world, the demand for AI chips is driving the trend towards bigger, smarter, and faster SoC designs. Consequently, low-power design, analysis, verification, and power signoff challenges are not getting any easier as chip designs deploy increasingly smaller geometries that dissipate more and more power. Despite this dilemma, the quest for further power reductions continues apace. ... » read more

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