Thanks For The Memories!


“I want to maximize the MAC count in my AI/ML accelerator block because the TOPs rating is what sells, but I need to cut back on memory to save cost,” said no successful chip designer, ever. Emphasis on “successful” in the above quote. It’s not a purely hypothetical quotation. We’ve heard it many times. Chip architects — or their marketing teams — try to squeeze as much brag-... » read more

Impact Of 3DHI On Aerospace And Government Applications


By Ian Land, Kenneth Larsen, and Rob Aitken With challenging size, weight, and power (SWaP) requirements, chip designs for aerospace, defense, and government applications are a unique breed. No surprise here, considering systems like satellites and submarines must operate reliably in the distinctly harsh environments of outer space and ocean depths, respectively. Given the SWaP criteria a... » read more

Is Transformer Fever Fading?


The hottest, buzziest thing bursts onto the scene and captures the attention of the business press and even the general public. Scads of articles and videos are published about The Hot Thing. And then, in the blink of an eye, the world’s attention shifts to the Next New Thing! Are we talking about the latest pop song that leads the Spotify streaming charts? Perhaps a new fashion trend that... » read more

How Can You Use ChatGPT For Software Testing?


All eyes have been on OpenAI and its brainchild ChatGPT in recent months. ChatGPT’s ability to understand and respond to complex instructions and deliver detailed responses to user prompts has led to an explosive rise in its popularity with the public. If you were to search online for “ChatGPT tips,” you can find content to help you use the tool to tailor resumes to job postings, create... » read more

Scaling Server Memory Performance To Meet The Demands Of AI


AI, whether we’re talking about the number of parameters used in training or the size of large language models (LLMs), continues to grow at a breathtaking rate. For over a decade, we’ve witnessed a 10X per year scaling. It’s a growth rate that puts pressure on every aspect of the computing stack: processing, memory, networking, you name it. The platform vendors are responding to the in... » read more

SoC Telemetry & Performance Analysis Using Statistical Profiling Extension


The Arm Statistical Profiling Extension (SPE) is an architectural feature designed for enhanced instruction execution profiling within Arm CPUs. This feature has been available since the introduction of the Neoverse N1 CPU platform in 2019, along with performance monitor units (PMUs) generally available in Arm CPUs. An important step in extracting value from capabilities like SPE and PMUs is th... » read more

Multi-Chiplet Marvels: Exploring Chip-Centric Thermal Analysis


The relationship between power consumption and thermal dynamics for chips is intricate. As power is consumed during the operation of a chip, it results in the generation of heat. This heat may dissipate from the device, metal routing, or the die itself, leading to increased temperatures on the chip. The dissipation process perpetually expends redundant energy, thereby compromising on the overal... » read more

Exploring The Facets Of Stray Light With Simulation


Seems like everywhere you look, there’s someone snapping a memorable group photo or perfect selfie with their phones. As the line between traditional and cellphone cameras continues to blur, manufacturers of these handheld devices are pressed to find the best combination of software and hardware to achieve image quality that was previously unthinkable. Of course, mobile photography has com... » read more

Getting Optimal PPA For HPC & AI Applications With Foundation IP


By Andrew Appleby, Xiaorui Hu, and Bhavana Chaurasia The demand for application-specific system-on-chips (SoCs) for compute applications is ever-increasing. Today, the diversity of requirements means there is a need for a rich set of compute solutions in a wide range of process technologies. The resulting products may have very different but demanding power, performance, and area (PPA) requi... » read more

AI-Driven Macro Placement Boosts PPA


In the era of EDA 4.0, artificial intelligence (AI) and machine learning (ML) are transforming what electronic design automation tools are capable of. For many of the challenges of physical IC design, AI can provide significant benefits to both the turnaround time and the quality of the design, as measured by performance, power, and area (PPA) metrics. One implementation step due for improve... » read more

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