Ensuring Multi-Die Package Quality And Reliability


Multi-die designs are gaining broader adoption in a wide variety of end applications, including high-performance computing, artificial intelligence (AI), automotive, and mobile. Despite clear advantages, there are new challenges that need to be addressed for successful multi-die realization. This article gives a high-level overview of the multi-die test challenges that go beyond the design p... » read more

Memory Implications Of Gen AI In Gaming


The global gaming market across hardware, software and services is on track to exceed annual revenues of $500B in 2025.1 That’s bigger by an order of magnitude than the combination of movies and music. On the cutting edge of that enormous market is open world gaming, where the driving goal is to give players the freedom to do anything they can imagine in a coherent and immersive environment. ... » read more

HBM3E: All About Bandwidth


The rapid rise in size and sophistication of AI/ML training models requires increasingly powerful hardware deployed in the data center and at the network edge. This growth in complexity and data stresses the existing infrastructure, driving the need for new and innovative processor architectures and associated memory subsystems. For example, even GPT-3 at 175 billion parameters is stressing the... » read more

Powering The Future Of Flight: Designing A Hydrogen-Powered eVTOL


A large, bustling city surrounds you — crowded streets and tall buildings reaching toward the sky. You’re late for an appointment. However, instead of hopping into a car, you look above for your ride: an electric vertical takeoff and landing (eVTOL) vehicle. It is a small aircraft that takes off and lands vertically like helicopters, uses sustainable electric propulsion systems, and is inte... » read more

ConvNext Runs 28X Faster Than Fallback


Two months ago in our blog we highlighted the fallacy of using a conventional NPU accelerator paired with a DSP or CPU for “fallback” operations. (Fallback Fails Spectacularly, May 2024). In that blog we calculated what the expected performance would be for a system with a DSP needing to perform the new operations found in one of today’s leading new ML networks – ConvNext. The result wa... » read more

224Gbps PHY For The Next Generation Of High Performance Computing


Large language models (LLMs) are experiencing an explosive growth in parameter count. Training these ever-larger models requires multiple accelerators to work together, and the bandwidth between these accelerators directly limits the size of trainable LLMs in High Performance Computing (HPC) environments. The correlation between the LLM size and data rates of interconnect technology herald a... » read more

A Guide To Rigid-Flex PCB Design


In today’s electronics industry, compact, efficient, and versatile PCBs are in high demand. Rigid-flex technology allows engineers to design boards that bend and flex without compromising performance or reliability. Mastering rigid-flex PCB design can be challenging due to its unique requirements. Whether you're an experienced designer expanding your skills or new to the field, this ar... » read more

Sensor Requirements For Developing Robust Environment Perception Systems


In recent years, sensor systems for environment perception have become increasingly important – whether for adaptive robotics, automated driving, industrial process and quality control, or condition monitoring. The aim is always to detect and interpret certain environmental characteristics. In doing so, it’s important to choose not only the right algorithm but also the right sensor or senso... » read more

PCIe 7.0: Speed, Flexibility & Efficiency For The AI Era


As the industry came together for PCI-SIG DevCon last month, one thing took center stage, and that was PCI Express 7.0. While still in the final stages of development, the world is certainly ready for this significant new milestone of the PCIe specification. Let’s look at how PCIe 7.0 is poised to address the escalating demands of AI, high-performance computing, and emerging data-intensive ap... » read more

PCIe 6.0 Address Translation Services: Verification Challenges And Strategies


Address Translation Services (ATS) is a mechanism in PCIe that allows devices to request address translations from the Input/Output Memory Management Unit (IOMMU). This is particularly important where devices need to access virtual memory. ATS enhances performance by enabling devices to cache translations, reducing the latency associated with memory access. This blog delves into the semantics ... » read more

← Older posts Newer posts →