category: Power Source

category: IoT, Security & Automotive

Changing The Meaning Of Sign-Off
By Muhammad Zakir - 07 Aug, 2014 - Comments: 0

Chip development teams are faced with an ever-increasing number of power integrity and reliability challenges these days, especially as designs adopt FinFET technology. Even those with the most thorough sign-off checks often encounter unexpected surprises that quickly turn into tape-out hurdles, or worse yet, extensive re-design. The best way to avoid this scenario and ensure a smoother sign-of... » read more

FinFET Based Designs: Reliability Verification Implications
By Aveek Sarkar - 10 Jul, 2014 - Comments: 1

Over the past few months, I’ve discussed various challenges associated with finFET-based designs. We all know that finFET devices enable design teams to operate their chips at significantly lower supply voltages with a very tight control on leakage current. But to control the overall power within a tight power budget, the challenge shifts to how the logic design is managed such that the overa... » read more

FinFET-Based Designs: Package Model Considerations
By Aveek Sarkar - 12 Jun, 2014 - Comments: 0

The use of FinFET devices in next-generation high-performance, low-power designs is a fundamental shift that is happening in the semiconductor industry. These devices through their smaller sizes, tighter Vth control and higher drive strengths enable higher performance and increased integration while reducing overall energy consumption. But along with their advantages these devices introduce and... » read more

FinFET-Based Designs: Power Sign-off Considerations
By Aveek Sarkar - 08 May, 2014 - Comments: 0

FinFET devices can operate at ultra-low sub-1V nominal supply voltage levels without impacting their delays. This allows for low power, higher performance designs needed for many of todays’ applications. These devices also have considerably higher drive strengths, allowing faster operating speeds. However, this can result in more localized di/dt current scenarios, and when coupled with more r... » read more

FinFET Based Designs: Power Analysis Considerations
By Aveek Sarkar - 10 Apr, 2014 - Comments: 2

Design teams working on mobile, computing, networking and other low power, high performance IPs and SoCs are migrating to FinFET-based technologies. However the benefits from their smaller sizes and the ability to deliver consistent performance at ultra-low sub-1V nominal supply voltage levels is outweighed by the worsening of power noise and reliability. As mentioned in an earlier blog on Powe... » read more

FinFET Reliability Issues
By Arvind Vel - 13 Mar, 2014 - Comments: 0

The 16nm FinFET node has introduced several new challenges in the IC design community. In addition to the complexity of power-noise and electromigration (EM) verification, thermal reliability has become a major concern for both chip and package designers. With the three-dimensional architecture of FinFET devices, new simulation approaches are being used to model thermal behavior of the die in o... » read more

ESD Signoff No Longer A “Nice to Have” In FinFET Design Era
By Karthik Srinivasan - 13 Feb, 2014 - Comments: 0

As the semiconductor industry transitions to finFETs, reliability challenges are increasing. ESD designers are challenged with new issues that would require significant rethinking and redesign of their existing ESD protection strategy. With significant complexity embedded in the silicon, failure analysis and silicon debug is challenging and time consuming even to the ESD experts. Technology ... » read more

Power Noise And Reliability Sign-off For The Sub-20nm FinFET Era
By Aveek Sarkar - 16 Jan, 2014 - Comments: 1

There is a greater focus on power noise and reliability simulations and sign-off as the complexity of SoC designs continue to increase with 100+ different voltage islands, clock and power gating techniques, and multiple IPs each operating on different clock and power domains, etc. The technology node migration from 40nm to 20nm is driving requirements for electro-migration (EM) and reliability ... » read more

How Reliable Are Interconnects In 16nm FinFET Designs?
By Arvind Vel - 05 Dec, 2013 - Comments: 0

The 16nm FinFET process node is rapidly becoming the preferred choice for advanced Integrated Circuit (IC) designs. The 16nm node’s lower standby leakage characteristics and increased drive strength capability enable IC designers to push the boundaries of low power – high performance designs. However, the choice of the node is also accompanied by reduced reliability margins, requiring desig... » read more

Current Generation Of FPGAs Pose New Power And Reliability Challenges
By Annapoorna Krishnaswamy - 07 Nov, 2013 - Comments: 0

Today’s FPGAs are being used in a wide variety of applications such as consumer electronics, computer and storage, automotive electronics, and mission critical applications. The flexibility to configure the device based on its need, the ability to reprogram its functions, and the hardware parallelism it offers to quickly process very large amounts of data are some of the reasons why off-the-s... » read more

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