The Growing Imperative Of Hardware Security Assurance In IP And SoC Design

By Pavani Jella - 24 Oct, 2024 - Comments: 0

In an era where technology permeates every aspect of our lives, the semiconductor industry serves as the backbone of innovation. From IoT devices to data centers, every piece of technology relies on integrated circuits (ICs) such as intellectual property (IP) cores and system on chips (SoCs). As these technologies become increasingly pervasive, the importance of hardware security assurance in t... » read more

Novel Molded FCBGA Package Platform For Highly Reliable Automotive Applications

By InRak Kim - 19 Sep, 2024 - Comments: 0

The conventional flip chip ball grid array (FCBGA) package platform has wide industry usage and provides high electrical performance. However, as high performance requirements increased, it encounters significant challenges. FCBGA packages frequently encounter underfill cracks after long term reliability or harsh reliability test conditions for automotive devices. Figure 1 shows the typical und... » read more

Reducing Transistor Capacitance At The 5nm Node Using A Source/Drain Contact Recess

By Pradeep Nanja - 19 Sep, 2024 - Comments: 0

In logic devices such as FinFETs (field-effect transistors), metal gate parasitic capacitance can negatively impact electrical performance. One potential way to reduce this parasitic capacitance is to add a source/drain contact (CT) recess step when building the source/drain metal structure. However, this additional structure can potentially increase the source/drain to via resistance. Using... » read more

Legacy Process Nodes Are Critical To Many Industries

By David Park - 19 Sep, 2024 - Comments: 0

As the semiconductor industry continues to push the boundaries of innovation with advanced nodes, it is easy to overlook the critical role that ICs manufactured at legacy process nodes play in our everyday lives. While the spotlight often shines on the leading-edge advancements of 5nm technology and below, it’s the mature nodes, those above 28nm and even above 130nm, that are the unsung ch... » read more

Semiconductor Photomask Market Poised For Another Year Of Growth

By Jan Willis - 19 Sep, 2024 - Comments: 0

The semiconductor photomask market, a crucial component in chip manufacturing, is on track for another year of robust growth. This growth trajectory is supported by a series of technological advancements and market trends that continue to drive innovation in the industry. As the annual SPIE Photomask Technology Conference approaches in early October in Monterey, California, it presents an oppor... » read more

Smart Manufacturing, Smart Data-AI, And Future Of Computing

By Melissa Grupen-Shemansky - 19 Sep, 2024 - Comments: 0

By Melissa Grupen-Shemansky, Pushkar Apte, and Mark da Silva Use of machine learning and artificial intelligence (ML/AI) is on an exponential rise across fields1 including all aspects of the semiconductor industry. In the last decade, the use of ML/AI exploded in the areas of speech recognition, facial recognition, smart phone features, search engines and now large language models like Chat... » read more

Current Characterization Of Various Cu RDL Designs In Wafer Level Packages (WLP)

By JeongMin Ju - 15 Aug, 2024 - Comments: 0

Copper (Cu) redistribution layer (RDL) technology is used to interconnect chips in various high current Wafer Level Packaging (WLP) applications. Typically, Cu RDLs with thicknesses of 5-9 µm and widths of 5-20 µm are used for high current sourcing. In this case, the temperature of the Cu RDL metal line increases due to the Joule heat generated when current passes through the metal line. If a... » read more

Bringing Curvilinear Data To Mask Data Prep

By Al Blais - 15 Aug, 2024 - Comments: 0

Advanced nodes that have been leveraging curvilinear correction with technologies such as ILT and curvilinear OPC are increasingly requiring the use of curvilinear masks to meet advanced feature size and pitch requirements. However, building curvilinear masks with standard OASIS file formats can come at the cost of large file sizes, increased turnaround time, and reduced quality of results. The... » read more

Improving Parasitic Capacitance In Next-Generation DRAM Devices

By Dempsey Deng - 15 Aug, 2024 - Comments: 0

As conventional DRAM devices continue to shrink, increases in parasitic capacitance at smaller dimensions can negatively impact device performance. New DRAM structures may be needed in the future, to lower total capacitance and achieve acceptable device performance. In this study, we compare the parasitic capacitance of a 6F2 honeycomb dynamic random-access memory (DRAM) device to the parasitic... » read more

Five Questions To Ask When Selecting A Temporary Bonding And Debonding System

By Jessica Albright - 15 Aug, 2024 - Comments: 0

High-bandwidth memory blocks (HBM), microprocessors, field-programmable gate arrays (FPGA), AI accelerators, and other devices used in advanced system-level packaging all rely on temporary bonding and debonding systems to shrink their footprint. Understanding which properties play the most crucial role in device reliability and efficient production will ensure you are maximizing your yield, whi... » read more

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Knowledge Centers
Entities, people and technologies explored

Shift Left Is The Tip Of The Iceberg

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NAND Flash Targets 1,000 Layers

New techniques go beyond improved deposition and etching, but challenges stack up, too.

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Pros and cons of a middle-ground chiplet assembly that combines 2.5D and 3D-IC.

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Focus is on letting engineers do much more with the same or fewer resources — and less drudgery.

by Karen Heyman

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The standard for high-bandwidth memory limits design freedom at many levels, but that is required for interoperability. What freedoms can be taken from other functions to make chiplets possible?

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Memory Fundamentals For Engineers

eBook: Nearly everything you need to know about memory, including detailed explanations of the different types of memory; how and where these are used today; what's changing, which memories are successful and which ones might be in the future; and the limitations of each memory type.

by The SE Staff

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