category: Blogs – MD

category: IoT, Security & Automotive

Photomask Market to Hit $3.35 billion in 2013
By Lara Chamness - 09 May, 2012 - Comments: 0

by Lara Chamness, senior market analyst, SEMI Industry Research and Statistics The worldwide semiconductor photomask market was $3.12 billion in 2011 and is forecasted to reach $3.35 billion in 2013. After reaching a market peak in 2010, the photomask market grew another 3 percent in 2011 to set another market high. The mask market is expected to grow 4 percent and 3 percent sequentially ove... » read more

Anchors Away – Anchoring and Seeding in Double Pattern Design.
By David Abercrombie - 02 May, 2012 - Comments: 0

David Abercrombie Many aspects of how double patterning (DP) affects the designer depend on the methodology used and the level of control the designer wants. One extreme in methodology and control is full two-layer design, in which the designer decomposes the entire design and tapes out two masks. The designer has complete control of the coloring, but all the responsibility and work as well. T... » read more

ST-Ericsson 28nm FD-SOI smartphone SOC, Q3 tape-out (interview)
By Various Writers - 24 Apr, 2012 - Comments: 0

ASN recently had a chance to talk to ST-Ericsson’s Chief Chip Architect Louis Tannyeres  about the move to 28nm FD-SOI for smartphones and tablet SOCs.  Take-away message:  FD-SOI solves – with less process complexity – scaling, leakage and variability issues to further shrink CMOS technology beyond 28nm. Here's what he said. ~~ [caption id="attachment_441" align="alignleft" wi... » read more

Incumbency rules! – in lithography as elsewhere.
By Michael Watts - 12 Apr, 2012 - Comments: 0

by Michael P.C. Watts If double patterning gets established is it just a stop gap until EUV ? This was the entertaining subject at coffee with my editor at semimd (the great thing about writing a free blog is that you get to buy your own coffee when you meet – and yes, we need to find something more fun to talk about !) We were discussing the latest in lithography that were the subject ... » read more

If Computers Could Write
By Chris Mack - 04 Apr, 2012 - Comments: 0

I have many titles.  Gentleman scientist.  Consultant.  Husband.  Dad.  Some are self-applied (the advantage of being my own boss), and some are earned.  One that I am proud of, and take seriously, is the title of “writer”.  Writing well is not easy, and I have the somewhat old-fashioned idea that I should only write if I have something worthwhile to say.  So when I do write somethi... » read more

Three DFM “Litho” Checkpoints at SMIC
By Mentor, a Siemens Business - 03 Apr, 2012 - Comments: 0

Design for manufacturing (DFM) has been an industry buzz word for several years, but now that it is an expected part of every design flow at 40nm and below, we are seeing how the concept of DFM can be successfully deployed. For example, Semiconductor Manufacturing International Corporation (SMIC), one of the world’s largest semiconductor foundries, has established a process for litho checking... » read more

Consortium Results (Part 3 of 3): 20nm FDSOI Comes Out Way Ahead
By Various Writers - 27 Mar, 2012 - Comments: 0

The results of the most recent SOI Consortium benchmarking study detail the interest of planar FD-SOI as early as the 28nm and 20nm technology nodes, in terms of performance, power and manufacturability. This 3-part blog series looks further at some of the implications. ~~ The SOI Industry Consortium announcement at the end of the year provided silicon proof that FD-SOI handily bea... » read more

Lithography: How Slow Can We Go?
By Chris Mack - 23 Mar, 2012 - Comments: 0

Moore’s Law has always been about economics:  if we follow the trend of Moore’s Law, we can reduce the cost per function for our integrated circuits, making chips more powerful for the same cost, or making chips of a given capability cheaper.  Historically, cost per function has decreased by about 29% per year, corresponding to a factor of 2 decrease in cost every two years.  There are s... » read more

FD-SOI – Consortium Results (Part 2 of 3): Power and Performance
By Various Writers - 21 Mar, 2012 - Comments: 0

The results of the most recent SOI Consortium benchmarking study detail the interest of planar FD-SOI as early as the 28nm and 20nm technology nodes, in terms of performance, power and manufacturability. This 3-part blog series looks further at some of the implications. ~~ Fully depleted transistor architectures such as Planar FD-SOI, FinFETs (which is also a fully-depleted technolog... » read more

ST-Ericsson NovaThor This Year, 28nm FDSOI, Soitec Wafers
By Various Writers - 14 Mar, 2012 - Comments: 0

Big and official FD-SOI news: Soitec has announced that the company is supplying the FD-SOI wafers for ST-Ericsson’s next-generation of NovaThor 8540 smartphone/tablet processors. Starting at the 28nm node, this marks the industry’s first industrialization of the new planar, fully-depleted technology on ultra-thin SOI wafers. Soitec has just issued an official press release, but ST-Eri... » read more

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