category: Blogs – PTES

category: IoT, Security & Automotive

Scan Pattern Portability From PSV To ATE To SLT To IST
By Ash Patel - 30 Jan, 2023 - Comments: 0

By Ash Patel and Karthik Natarajan Chip testing has become increasingly complex due to the number of variables impacting designs – from design size and complexity, to high transistor counts on advanced technology nodes, to 2.5D/3D packaging, to manufacturing variability. All of these combine to make testing today's chips and packages more complicated than ever before. The number of test pa... » read more

Emerging Technologies Are Driving System Level Test Adoption
By Natalian Z. Der - 10 Jan, 2023 - Comments: 0

With the size of semiconductor transistors decreasing and chip complexity increasing exponentially, semiconductor test has become essential to ensuring that only high-quality products go to market. With the introduction of more rigorous acceptable quality level (AQL) certifications, test methods must constantly evolve to meet these standards, and system level test (SLT) and traditional test... » read more

Industrial Solutions For Machine-Learning-Enabled Yield Optimization And Test
By Sonny Banwari - 10 Jan, 2023 - Comments: 0

This article summarizes the content of a paper developed and presented by Advantest at ETS 2022. By Sonny Banwari and Matthias Sauer According to market research firm Gartner, Inc., in assessing the completion rate of data science projects, as well as the bottom-line value they generate for their companies, only between 15 and 20 percent of these projects are ever completed. Moreover, of ... » read more

Metrology Sampling Plans Are Key For Device Analytics And Traceability
By Mike McIntyre - 06 Dec, 2022 - Comments: 0

A mother steps on the brakes, bringing her car to a stop as she drops her kids off for dance lessons. At the time, she doesn't notice anything wrong, but when she takes her car in for its regular service appointment, the mechanic conducts a diagnostic check and discovers that the primary brake system on the car had failed because of a faulty braking controller without anyone realizing it. Fortu... » read more

Manage Your Risk In RISC-V
By Peter Shields - 06 Dec, 2022 - Comments: 0

Adoption of RISC-V processors is accelerating. This technology, like everything, comes with benefits and risks. The open standard means freedom for many developers, but success depends on the development of a support ecosystem around RISC-V. Industry collaboration is making broad adoption of RISC-V possible, and one example is the introduction of efficient trace for RISC-V cores. When incorp... » read more

Testability Analysis Based On Ever-Evolving Technology
By Pawini Mahajan - 06 Dec, 2022 - Comments: 0

The complexity of system-on-chip (SoC) designs continues to grow, so the corresponding design-for-test (DFT) logic required for manufacturing has become more advanced. Design teams are challenged by high gate counts and an array of internally developed and third-party IP integrated into their designs. Understanding if one can create high-quality manufacturing tests for these complex designs mus... » read more

Ensuring Your Semiconductor Test Equipment Is Protected From Rising Cybersecurity Threats
By Eli Roth - 06 Dec, 2022 - Comments: 0

Cybersecurity threats pose risks to your business every day and can attack every aspect of your operation, and these threats are only increasing. According to IBM Security’s Cost of a Data Breach Report, in 2021, the average total cost of a data breach increased by nearly 10% year over year, from $3.86M to $4.24M – the largest single year cost increase in the last seven years. Sourc... » read more

A Customized Low-Cost Approach For S-Parameter Validation Of ATE Test Fixtures
By Zhenhua Chen - 06 Dec, 2022 - Comments: 0

This article summarizes the content of a paper jointly developed and presented by Advantest and Infineon at TestConX 2022. Device under test (DUT) fixtures for ATE systems pose several verification challenges. Users need to measure the DUT test fixture quickly and easily, while making sure the measurements mimic the ATE-to-test-fixture interface performance and determining how to handle DUT ... » read more

Heterogeneous Integration: Correcting Overlay Errors On Advanced Integrated Circuit Substrates (AICS)
By John Chang - 08 Nov, 2022 - Comments: 0

By John Chang, with Corey Shay, James Webb, and Timothy Chang For high-performance computing, artificial intelligence, and data centers, the path ahead is certain, but with it comes a change in substrate format and processing requirements. Instead of relying on the quest for the next technology node to bring about future device performance gains, manufacturers are charting a future based inc... » read more

How To Improve Yield Ramp For New Designs And Technology Nodes
By Jayant D'Souza - 08 Nov, 2022 - Comments: 0

The complicated silicon defect types and defect distribution of new IC manufacturing technologies can result in very low yield for new designs and technology nodes. During technology qualification using test chips, scan chain failures account for most of the chip failures. Diagnosing those scan chain defects is a powerful way to uncover new and systematic defects. The chip maker’s goal is ... » read more

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