How Qualcomm Got Faster Signoff DRC Convergence


Qualcomm Incorporated designs and markets wireless telecommunications products and services that are the foundational technologies that others build upon, from mobile processors to embedded platforms, Bluetooth products, and cellular modems. In the fast-moving mobile phone market in which Qualcomm competes, companies who can get to market more quickly gain a strong competitive advantage, along ... » read more

The Time Is Now For A Common Model Interface


By Ahmed Ramadan and Greg Curtis Driven by consumer demand for “cheaper, faster, and better,” the semiconductor industry is continually pushing the migration to smaller process geometries. This continued scaling of complex designs into advanced process nodes is critical for applications ranging from high-performance computing to low-power mobile devices. In the past, products like sma... » read more

Verifying AI Designs Thoroughly And Quickly


You can’t turn around these days without seeing a reference to AI – even as a consumer. AI, or artificial intelligence, is hot due to the new machine-learning (ML) techniques that are evolving daily. It’s often cited as one of the critical markets for electronics purveyors, but it’s not really a market: it’s a technology. And it’s quietly – or not so quietly – moving into many, ... » read more

Five Rules For Correlating Rule-based And Field Solver Parasitic Extraction Results


There comes a time at every foundry and IC design company when it becomes necessary to run a correlation between a rule-based parasitic extraction (PEX) table and a field solver solution. And when that time arrives, there are a few (five, to be precise) details that will help ensure the correlation produces accurate results. But before we get to those, let’s do a quick refresh on PEX techniqu... » read more

Cracking The Mixed-Signal Verification Code


Rapid digitization in IoT, automotive, industrial, and communication industry segments are fueling semiconductor industry growth. This growth follows the “More than Moore” paradigm, where new design starts are spread across mature to advanced manufacturing nodes based on end-application targets. With this digitalization, data has become the most valuable resource. Mixed-signal designs pl... » read more

Improving Library Characterization Quality And Runtime With Machine Learning


By Megan Marsh and Wei-Lii Tan Today’s semiconductor applications, ranging from advanced sensory applications, IoT, edge computing devices, high performance computing, to dedicated A.I. chips, are constantly pushing the boundaries of attainable power, performance, and area (PPA) metrics. The race to design and ship these innovative devices has resulted in a focused, time-to-market-driven e... » read more

Next-Generation Liberty Verification And Debugging


Accurate library characterization is a crucial step for modern chip design and verification. For full-chip designs with billions of transistors, timing sign-off through simulation is unfeasible due to run-time and memory constraints. Instead, a scalable methodology using static timing analysis (STA) is required. This methodology uses the Liberty file to encapsulate library characteristics such ... » read more

Digital IC Bring-Up With A Bench-Top Environment


One of the hottest markets for IC today is artificial intelligence (AI). The designs for AI chips are also among the largest and most complex, with billions of transistors, thousands of memory instances, and complex design-for-test (DFT) implementations with unique bring up and debug requirements. At this point, the volume of new AI chips is relatively low, but time-to-market is of paramount im... » read more

Synthesizing Computer Vision Designs To Hardware


Computer vision is one of the hottest markets in electronic design today. Digital processing of images and video with complex algorithms in order to interpret meaning has almost as many applications and markets as there are uses for the human eye. The biggest problem that designers face is that the computer vision system requirements and algorithms change quickly and often. Even the targ... » read more

Raising The Bar On Flat CDC Verification With Hierarchical Data Models


By Ashish Hari, Aditya Vij, and Ping Yeung Traditionally, clock domain crossing (CDC) verification at the SoC level has relied on flat simulation runs. But flat CDC verification has run out of gas. Largely because of the increase in the number of asynchronous clocks in larger, faster, more complex designs. Flat CDC runs are too performance intensive, time-consuming, and result in high noise.... » read more

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