3D Extraction Necessities For 5nm And Below


For most of my career in product marketing I’ve been focused on Static Timing Analysis (STA). It was, and still is, an area with a diverse set of topics including graph based analysis and path based analysis, on-chip variation modeling, delay calculation, evolving library models, etc. During those years I always understood that  parasitic extraction was a crucial element of STA and more impo... » read more

It Takes A Village… To Develop And Verify SoCs


In my last blog post from 2017, “Design Chains Will Drive The Top 5 EDA Trends In 2018,” I had pointed to the importance of ecosystems for electronics development in general. From an EDA perspective, it also takes a village to shepherd the actual chip development with its complex verification and software development tasks. And the types of partnerships often depend on the application domai... » read more

Analyzing Data Differently


Data analysis is often a very time consuming process for a hardware design or verification engineer. We always end up using the waveform viewer which may not be very efficient in giving us a high-level overview of what we’re looking for. Data that is spread across a long simulation cycle is very hard to visualize on the waveform. Whenever I have to analyze a huge chunk of data, I always wonde... » read more

In Case You Missed It


We recently held two very successful seminars in Tokyo and Shanghai. Samsung Memory presented their HBM2 solutions, Samsung Foundry talked about their advanced 14nm FinFET solutions, ASE Group reviewed their advanced 2.5D packaging solutions, eSilicon presented our ASIC and 2.5D design/implementation and IP solutions, Rambus detailed their high-performance SerDes solutions and Northwest Logic p... » read more

Building In Functional Safety At The Lowest Hardware Levels Supports Autonomous Driving’s Future


Long before automotive electronic system designers chose artificial intelligence and machine learning as the path toward the future of autonomous driving’s future, it was clear that high-performance computing platforms typically found in data center systems clearly were not going to provide all the answers. Automotive system designers place more emphasis on functional safety and resilience, w... » read more

Smarter DFT Infrastructure And Automation Emerge As Keys To Managing DFT Design Scaling


By Ron Press and Vidya Neerkundar The reality of DFT for large and complex SoCs has introduced new risk into design schedules. DFT teams end up in the critical path to tape out while waiting for portions of the design to be complete, and there are more DFT integration steps than ever before. The traditional approaches to DFT work on huge designs pose problems of repeatability and reliability... » read more

Bulletproofing Virtual Prototypes


The big benefits of virtual prototyping methods are that they don’t rely on the availability of RTL or physical hardware. Instead they utilize modes of the future SoC. These models are typically lightweight and optimized for their use case, which is important in regards of simulation speed, modeling and testing effort. Model quality is a key concern, as the virtual prototyping end user accept... » read more

What’s Next?


We just concluded two very successful seminars in Tokyo and Shanghai. Samsung Memory presented their HBM2 solutions, Samsung Foundry talked about their advanced 14nm FinFET solutions, ASE Group reviewed their advanced 2.5D packaging solutions, eSilicon presented our ASIC and 2.5D design/implementation and IP solutions, Rambus detailed their high-performance SerDes solutions and Northwest Logic ... » read more

Design Chains Will Drive The Top 5 EDA Trends In 2018


In my prediction piece last year, I made seven trend predictions. Looking back, I did very well compared to what actually happened. For 2018, I am cutting it down to five trends that will impact EDA, but in my mind a lot of the trends will be driven by the ever-evolving ecosystem of design chains from IP though semiconductor to systems and to OEMs. While HBO’s 'Game of Thrones' comes to a con... » read more

Using Formal To Solve The World’s Hardest Sudoku


It’s no secret that the OneSpin team loves contests. Last year around this time, we set a challenge to engineers everywhere: solve the famous Einstein’s Riddle using a formal tool. After an enthusiastic response, we decided to make the holiday puzzle an annual event, with a different subject area each year. Our engineering team was challenged to come up with a new topic, and my idea, whi... » read more

← Older posts Newer posts →