category: Blogs – SLD

category: IoT, Security & Automotive

Top 15 Integrating Points In The Continuum Of Verification Engines
By Frank Schirrmeister - 30 Jul, 2015 - Comments: 0

The integration game between the different verification engines, dynamic and static, is in full swing. Jim Hogan talked about the dynamic engines that he dubbed “COVE”, and I recently pointed out a very specific adoption of COVE in my review of some customer examples at DAC 2015 in “Use Model Versatility Is Key for Emulation Returns on Investment”. Here are my top 15 integrating poin... » read more

Prototyping To Help You Win The Battle
By Tom De Schutter - 30 Jul, 2015 - Comments: 0

Lately, my children and I are closely following a new show on ABC called “Battlebots”. The concept is as simple as it is cool—have a massive bulletproof arena where two remote-controlled robots battle it out until one is knocked out or the time is up (and a jury decides the winner). The battles are all about making physical contact with the other robot to either directly deal them damage ... » read more

Consolidation Creates Confusion
By Mike Gianfagna - 30 Jul, 2015 - Comments: 0

Consolidation in any industry is a sign of maturation. Diverse business models converge to the ones that really work. Supply and demand find equilibrium with a right-sized supply base. And generally, the fittest survive. The semiconductor industry is somewhere around a half-century old, so consolidation in this industry is to be expected, and we have certainly seen some consolidation of late. ... » read more

7 Ways to Assess Semiconductor IP Quality
By Kurt Shuler - 30 Jul, 2015 - Comments: 0

Design teams today are struggling with the quality of semiconductor intellectual property. These teams want first-pass success for SoC creation, but that is becoming increasingly difficult to achieve—especially with highly configurable IP. Yet the more configurable the IP is, the more desirable it is as a differentiator. And if not developed correctly, it may be even more risky than non-confi... » read more

Why DSA Is Cost Effective For 7nm And Below
By Yuansheng Ma - 30 Jul, 2015 - Comments: 0

The upcoming 7nm process node presents tough challenges both for printability and cost. At 7nm and below, multi-patterning is required, which makes the manufacturing process more expensive by requiring more masks. To control costs, any alternative technology that provides equivalent yields with fewer patterning steps should be explored. One promising option is to use directed self-assembly (... » read more

Technology Tsunami Approaches
By Brian Bailey - 27 Jul, 2015 - Comments: 0

How many times have we heard the saying that technology advancements are accelerating and that inevitably the older generation will have increasing problems keeping up with the new advancements? This happened to me with software development methodologies over fifteen years ago. I still program, when people actually let me, using basically the same techniques I learned when I was in my teens.... » read more

UVM: What’s Stopping You?
By Doug Amos - 02 Jul, 2015 - Comments: 0

These days, verification of the most complex designs is performed using a standard verification methodology, probably SystemVerilog-based [gettech id="31055" comment="UVM"]. Many verification teams have ramped up on UVM, but others have yet to take the plunge. Why is that? And how big a “plunge” is it, anyway? If UVM is as great as all that, then why hasn’t everybody adopted it already... » read more

Intel Plus Altera
By Ed Sperling - 25 Jun, 2015 - Comments: 0

Since the Intel-Altera deal reached the handshake phase earlier this month, there have been a lot of theories being forwarded and a lot of questions being raised. And there have been very few answers, in part because the deal isn't finalized yet and in part because this marriage will take time to play out in the market—maybe years. But along with the GlobalFoundries-IBM pairing, this is th... » read more

Tear Down The Wall Between Front-End And Back-End Teams
By Kurt Shuler - 25 Jun, 2015 - Comments: 1

As complexity of system-on-chip devices increases, it's becoming imperative for design teams and organizations to re-examine how they work with one another in order to improve productivity. One giant step in this direction is to bridge the divide between the front-end design process and the physical back-end design process. We often refer to this as a figurative “wall,” but there is real... » read more

Towards A Metric To Measure Verification Computing Efficiency
By Frank Schirrmeister - 25 Jun, 2015 - Comments: 1

Thinking back about DAC 2015 in San Francisco earlier this month, I am happy that at least some of my predictions came true—there was clearly a trend towards making verification smarter. However, one thing struck me while hearing all the discussions on connecting engines is what Jim Hogan called the continuum of verification engines (COVE)—and what we at Cadence call the system development ... » read more

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