category: Low Power-High Performance

category: IoT, Security & Automotive

Optimizing For Energy In Physical Design
By Pierre-Alexandre Bou-Ach - 10 Sep, 2020 - Comments: 0

Energy is a precious resource, which should not be wasted. Energy drives economies and sustains societies. Predictions show that the energy of electronics may soon consume 20% to 33% of the global energy supply, as it is highlighted in this blog post about "Design and Manufacturing in 2030" from Greg Yeric, fellow at Arm. Energy efficiency is such an important global issue that it is ... » read more

Is DVFS Worth The Effort?
By Brian Bailey - 10 Sep, 2020 - Comments: 2

Almost all designs have become power-aware and are being forced to consider every power saving technique, but not all of them are yielding the expected results. Moreover, they can add significant complexity into designs, increasing the time it takes to get to tapeout and boosting up the cost. Dynamic voltage and frequency scaling (DVFS) is one such power and energy saving technique now being... » read more

A Historical Case For Precision
By Lee Vick - 10 Sep, 2020 - Comments: 0

We take for granted today the staggering precision of modern technology. Cars, electronics, robots, and medical equipment all come off the factory floor composed of effortlessly interchangeable parts, but this was not always the case. In the late 18th century most things that required any kind of precision were made by hand, one notable example being the flintlock musket. You see, back then if ... » read more

Dealing With Device Aging At Advanced Nodes
By Ann Mutschler - 10 Sep, 2020 - Comments: 0

Premature aging of circuits is becoming troublesome at advanced nodes, where it increasingly is complicated by new market demands, more stress from heat, and tighter tolerances due to increased density and thinner dielectrics. In the past, aging and stress largely were separate challenges. Those lines are starting to blur for a number of reasons. Among them: In automotive, advanced-node... » read more

OIP Ecosystem Forum 2020
By Paul McLellan - 10 Sep, 2020 - Comments: 0

Last Tuesday was the virtual TSMC OIP Ecosystem Forum. Apart from being virtual, the format was similar to the usual. Cliff Hou, Senior Vice President of Technology Development, opened the day with a summary of where everything is in the ecosystem around each of the new processes. There were then three keynotes by the leaders of the three big EDA companies. That was followed by more technical ... » read more

Learn How To Streamline Design Flows And Reduce Design Cost
By Marc Swinnen - 10 Sep, 2020 - Comments: 0

I’m excited to announce that general registration is now open for the new Ansys IDEAS Digital Forum!  IDEAS, hosted by Ansys Semiconductor, is a virtual gathering of top industry executives, thought leaders, and designers from some of the biggest IP, chip design, semiconductor foundry and electronic system companies in the world. Log in to IDEAS to join with your peers to listen to industry ... » read more

Compiling And Optimizing Neural Nets
By Bryon Moyer - 10 Sep, 2020 - Comments: 0

Edge inference engines often run a slimmed-down real-time engine that interprets a neural-network model, invoking kernels as it goes. But higher performance can be achieved by pre-compiling the model and running it directly, with no interpretation — as long as the use case permits it. At compile time, optimizations are possible that wouldn’t be available if interpreting. By quantizing au... » read more

Efficient Sensitivity-Aware Assessment Of High-Speed Links Using PCE And Implications For COM
By Mentor, a Siemens Business - 09 Sep, 2020 - Comments: 0

This technical white paper, originally presented at DesignCon, investigates the challenges of increased data rates and reduced margins in high-speed link design. Section 1: Introduction Section 2: State of the Art Link Evaluation and Assessment of Parameter Variability Section 3: Proposed Modeling Framework Section 4: Sensitivity Analysis of a High-Speed Interconnect Section 5: Conclusio... » read more

How ML Enables Cadence Digital Tools To Deliver Better PPA
By Cadence - 09 Sep, 2020 - Comments: 0

Artificial intelligence (AI) and machine learning (ML) are emerging as powerful new ways to do old things more efficiently, which is the benchmark that any new and potentially disruptive technology must meet. In chip design, results are measured in many different ways, but common metrics are power (consumed), performance (provided), and area (required), collectively referred to as PPA. These me... » read more

Early Verification Of Multi-Cycle Paths And False Paths In Simulation
By Synopsys - 09 Sep, 2020 - Comments: 0

Timing closure is a critical step in the chip development process. The performance and timing of a design must be verified, and any violations must be investigated and resolved. This includes the specification and verification of timing exceptions. This white paper focuses on false paths and multi-cycle paths, the use of Synopsys Design Constraints (SDC) to specify these exceptions, and the “... » read more

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