category: Low Power-High Performance

category: IoT, Security & Automotive

A Performance Analysis Of The First Generation Of HPC‐Optimized Arm Processors
By Arm - 09 Sep, 2020 - Comments: 0

In this paper, the authors present performance results from Isambard, the first production supercomputer to be based on Arm CPUs that have been optimized specifically for HPC. Isambard is the first Cray XC50 “Scout” system, combining Cavium ThunderX2 Arm‐based CPUs with Cray's Aries interconnect. The full Isambard system contained over 10,000 Arm cores. In this work, we present node‐lev... » read more

From Data Center To End Device: AI/ML Inferencing With GDDR6
By Rambus - 09 Sep, 2020 - Comments: 0

Created to support 3D gaming on consoles and PCs, GDDR packs performance that makes it an ideal solution for AI/ML inferencing. As inferencing migrates from the heart of the data center to the network edge, and ultimately to a broad range of AI-powered IoT devices, GDDR memory’s combination of high bandwidth, low latency, power efficiency and suitability for high-volume applications will be i... » read more

Electro-Thermal Signoff For Next Gen 3DICs
By Ansys - 09 Sep, 2020 - Comments: 0

Multi-die designs, 2.5D and 3D, have been rising in popularity as they offer tremendously increased levels of integration, a smaller footprint, performance gains and more. While they are attractive for many applications, they also create design bottlenecks in the areas of thermal management and power delivery. For 3DICs, in addition to the complex SoC/PCB interactions seen in their 2D counterpa... » read more

A Summary Of Piezoelectric Energy Harvesting For Autonomous Smart Structures
By Fraunhofer IIS/EAS - 09 Sep, 2020 - Comments: 0

The technology of energy harvesting has great potential to enable energy autonomy of wireless sensors. The drop of power requirements of micro-electronic devices allows confidence that piezoelectric energy harvesting (PEH) is able to reliably power a wireless sensor network (WSN). The present work summarizes results of ongoing research in the field of PEH. With the aid of a performance metric a... » read more

Power/Performance Bits: Sept. 9
By Jesse Allen - 09 Sep, 2020 - Comments: 0

Smaller, cheaper integrated photonics Researchers from the University of California Santa Barbara, California Institute of Technology (Caltech), and Ecole Polytechnique Fédérale de Lausanne (EPFL) developed a way to integrate an optical frequency comb on a silicon photonic chip. Optical frequency combs are collections of equally spaced frequencies of laser light (so called because when pl... » read more

Power/Performance Bits: Sept. 1
By Jesse Allen - 01 Sep, 2020 - Comments: 0

Cooling sensors with lasers Researchers at the University of Washington developed a way to cool a solid semiconductor sensor component with an infrared laser. The laser was able to cool the solid semiconductor by at least 20 degrees C, or 36 F, below room temperature. The device uses a cantilever, similar to a diving board, that can oscillate in response to thermal energy at room temperatur... » read more

Wireless Power Market Heats Up
By Bryon Moyer - 26 Aug, 2020 - Comments: 2

The wireless power market is in flux as established technologies meet newer approaches. Old standards battles have simmered somewhat, but competing messages remain. What the public ends up using will depend heavily on public charging infrastructure, but the stakes are significant. The market for battery chargers is forecast to reach $25B by 2022. Most of those chargers plug into the wall, bu... » read more

What Happened To Execute-in-Place?
By Bryon Moyer - 25 Aug, 2020 - Comments: 0

Executing code directly from non-volatile memory, where it is stored, greatly simplifies compute architectures — especially for simple embedded devices like microcontrollers (MCUs). However, the divergence of memory and logic processes has made that nearly impossible today. The term “execute-in-place,” or ”XIP,” originated with the embedded NOR memory in MCUs that made XIP viable. ... » read more

Power/Performance Bits: Aug. 25
By Jesse Allen - 25 Aug, 2020 - Comments: 0

AI architecture optimization Researchers at Rice University, Stanford University, University of California Santa Barbara, and Texas A&M University proposed two complementary methods for optimizing data-centric processing. The first, called TIMELY, is an architecture developed for “processing-in-memory” (PIM). A promising PIM platform is resistive random access memory, or ReRAM. Whil... » read more

Monitoring Chips After Manufacturing
By Brian Bailey - 19 Aug, 2020 - Comments: 2

New regulations and variability of advanced process nodes are forcing chip designers to insert additional capabilities in silicon to help with comprehension, debug, analytics, safety, security, and design optimization. The impact of this will be far-reaching as the industry discusses what capabilities can be shared between these divergent tasks, the amount of silicon area to dedicate to it, ... » read more

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