category: Low Power-High Performance

category: IoT, Security & Automotive

Research Bits: June 9
By Jesse Allen - 09 Jun, 2025 - Comments: 0

InGaOx GAA transistor Researchers from the University of Tokyo created a gate-all-around transistor made from gallium-doped indium oxide (InGaOx). Doping indium oxide with gallium suppressed oxygen vacancies, improving transistor reliability. "We wanted our crystalline oxide transistor to feature a 'gate-all-around' structure, whereby the gate, which turns the current on or off, surrounds t... » read more

Connecting AI Accelerators
By Ann Mutschler - 04 Jun, 2025 - Comments: 0

Experts At The Table: Semiconductor Engineering sat down to discuss the various ways that AI accelerators are being applied today with Marc Meunier, director of ecosystem development at Arm; Jason Lawley, director of product marketing for AI IP at Cadence; Paul Karazuba, vice president of marketing at Expedera; Alexander Petr, senior director at Keysight; Steve Roddy, chief marketing office... » read more

Research Bits: June 3
By Jesse Allen - 03 Jun, 2025 - Comments: 0

Imaging power electronics Researchers from the Institute of Science Tokyo, Harvard University, and Hitachi used diamond quantum sensors to analyze the magnetization response of soft magnetic materials used in power electronics. The method can simultaneously image both the amplitude and phase of AC stray fields over a wide frequency range up to 2.3 MHz. It uses a diamond quantum sensor with ... » read more

Research Bits: May 27
By Jesse Allen - 27 May, 2025 - Comments: 0

Tracking ferroelectric domain walls Researchers from Oak Ridge National Laboratory and National Cheng Kung University developed a technique called scanning oscillator piezoresponse force microscopy to observe how domain walls move in ferroelectric materials under rapidly fluctuating electric fields. “Domain walls can have completely different properties from the neighboring domains they s... » read more

Future-proofing AI Models
By Ann Mutschler - 21 May, 2025 - Comments: 0

Experts At The Table: Making sure AI accelerators can be updated for future requirements is becoming essential due to the rapid introduction of new models. Semiconductor Engineering sat down to discuss the challenges of future-proofing these designs with Marc Meunier, director of ecosystem development at Arm; Jason Lawley, director of product marketing for AI IP at Cadence; Paul Karazuba, vic... » read more

Research Bits: May 20
By Jesse Allen - 20 May, 2025 - Comments: 0

Smart t-shirt with sound waves Researchers at ETH Zurich developed a smart textile that uses acoustic waves passed through glass fibers to measure touch, pressure, and movement. The researchers said that using acoustic waves rather than electronics makes measurements more precise with low power consumption and the textiles lighter, more breathable, and easier to wash. It also uses readily avai... » read more

Intent Meets Implementation
By Siemens EDA - 15 May, 2025 - Comments: 0

Power efficiency has become a must-have in today’s ASIC and SoC designs. It’s no longer just about squeezing out more performance. It’s about doing so without draining the battery, wasting energy or overheating the system. Whether the chip is headed for a smartphone, a server rack in an AI datacenter or the control system of an autonomous vehicle, managing power wisely is as critical as m... » read more

Optimizing Analog With Layout In The Loop
By Benjamin Prautsch - 15 May, 2025 - Comments: 0

Meeting high-performance requirements at low power isn’t easy. What is already challenging in digital is even more complex in analog. After specification and block-level system concept, the analog design flow typically spends considerable time coming up with well-working schematic-level topologies. However, once layout parasitics become apparent through parasitic extraction, the seemingly opt... » read more

Best Practices For Power-Aware Verification: Because Designing For Low Power Is Only Half The Battle
By Chandu Challapalli - 15 May, 2025 - Comments: 0

As modern chips push the limits of power efficiency, power management has become a top priority. With today’s increasingly complex devices, verifying power intent isn’t just a technical requirement. It’s a necessity for building reliable silicon. One of the most important lessons learned in recent years is that RTL and power intent must evolve together. Treating power intent as a post... » read more

HBM4 Elevates AI Training Performance To New Heights
By Nidish Kamath - 15 May, 2025 - Comments: 0

Generative and Agentic AI are pushing an extremely rapid evolution of computing technology. With leading-edge LLMs now in excess of a trillion parameters, training takes an enormous amount of computing capacity, and state-of-the-art training clusters can employ more than 100,000 GPUs. High Bandwidth Memory (HBM) provides the vast memory bandwidth and capacity needed for these demanding AI train... » read more

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