Research Bits: Jan. 8


High mobility graphene Researchers at the Georgia Institute of Technology and Tianjin University created a functional semiconductor made from graphene that is compatible with conventional microelectronics processing methods. "We now have an extremely robust graphene semiconductor with 10 times the mobility of silicon, and which also has unique properties not available in silicon," said Walt... » read more

SRAM’s Role In Emerging Memories


Experts at the Table — Part 3: Semiconductor Engineering sat down to talk about AI, the latest issues in SRAM, and the potential impact of new types of memory, with Tony Chan Carusone, CTO at Alphawave Semi; Steve Roddy, chief marketing officer at Quadric; and Jongsin Yun, memory technologist at Siemens EDA. What follows are excerpts of that conversation. Part one of this conversation can be ... » read more

Research Bits: Jan. 2


Synaptic transistor Researchers from Northwestern University, Boston College, and MIT developed a synaptic transistor that simultaneously processes and stores information similar to the human brain. The team said the transistor goes beyond simple machine learning tasks to categorize data and is capable of performing associative learning. The new device is stable at room temperatures. It als... » read more

Analog Design Complicates Voltage Droop


Experts at the Table: Semiconductor Engineering sat down to talk about voltage droop in analog and mixed-signal designs, and the need for multi-vendor tool interoperability and more precision, with Bill Mullen, distinguished engineer at Ansys; Rajat Chaudhry, product management group director at Cadence; Heidi Barnes, senior applications engineer at Keysight; Venkatesh Santhanagopalan, product ... » read more

Research Bits: Dec. 18


Stacking 2D layers for AI processing Researchers from Washington University in St. Louis, MIT, Yonsei University, Inha University, Georgia Institute of Technology, and the University of Notre Dame demonstrated monolithic 3D integration of layered 2D material, creating a novel AI processing hardware that integrates sensing, signal processing, and AI computing functions into a single chip. Th... » read more

SAP: A Secure Low-Latency Protocol for Mitigating High Computation Overhead in WI-FI Networks


The increase in popularity of wireless networks in industrial, embedded, medical and public sectors has made them an appealing attack surface for attackers who exploit the vulnerabilities in network protocols to launch attacks such as Evil Twin, Man-in-the-middle, sniffing, etc., which may result in economic and non-economic losses. To protect wireless networks against such attacks, IEEE 802.11... » read more

Using Real Workloads To Assess Thermal Impacts


Thermal analysis is being driven much further left in the design, fueled by demand for increased transistor density and more features on a chip or in a package, as well as the unique ways the various components may be exercised or stressed. However, getting a clear picture of the thermal activity in advanced-node chips and packages is extremely complex, and it can vary significantly by use c... » read more

BYO NPU Benchmarks


In our last blog post, we highlighted the ways that NPU vendors can shade the truth about performance on benchmark networks such that comparing common performance scores such as “Resnet50 Inferences / Second” can be a futile exercise. But there is a straight-forward, low-investment method for an IP evaluator to short-circuit all the vendor shenanigans and get a solid apples-to-apples result... » read more

Data Formats For Inference On The Edge


AI/ML training traditionally has been performed using floating point data formats, primarily because that is what was available. But this usually isn't a viable option for inference on the edge, where more compact data formats are needed to reduce area and power. Compact data formats use less space, which is important in edge devices, but the bigger concern is the power needed to move around... » read more

The Journey To Exascale Computing And Beyond


High performance computing witnessed one of its most ambitious leaps forward with the development of the US supercomputer “Frontier.” As Scott Atchley from Oak Ridge National Laboratory discussed at Supercomputing 23 (SC23) in Denver last month, the Frontier had the ambitious goal of achieving performance levels 1000 times higher than the petascale systems that preceded it, while also stayi... » read more

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