category: Low Power-High Performance

category: IoT, Security & Automotive

Analog Design Complicates Voltage Droop
By Ann Mutschler - 27 Dec, 2023 - Comments: 0

Experts at the Table: Semiconductor Engineering sat down to talk about voltage droop in analog and mixed-signal designs, and the need for multi-vendor tool interoperability and more precision, with Bill Mullen, distinguished engineer at Ansys; Rajat Chaudhry, product management group director at Cadence; Heidi Barnes, senior applications engineer at Keysight; Venkatesh Santhanagopalan, product ... » read more

Research Bits: Dec. 18
By Jesse Allen - 18 Dec, 2023 - Comments: 0

Stacking 2D layers for AI processing Researchers from Washington University in St. Louis, MIT, Yonsei University, Inha University, Georgia Institute of Technology, and the University of Notre Dame demonstrated monolithic 3D integration of layered 2D material, creating a novel AI processing hardware that integrates sensing, signal processing, and AI computing functions into a single chip. Th... » read more

SAP: A Secure Low-Latency Protocol for Mitigating High Computation Overhead in WI-FI Networks
By Fraunhofer IIS/EAS - 14 Dec, 2023 - Comments: 0

The increase in popularity of wireless networks in industrial, embedded, medical and public sectors has made them an appealing attack surface for attackers who exploit the vulnerabilities in network protocols to launch attacks such as Evil Twin, Man-in-the-middle, sniffing, etc., which may result in economic and non-economic losses. To protect wireless networks against such attacks, IEEE 802.11... » read more

Using Real Workloads To Assess Thermal Impacts
By Ann Mutschler - 14 Dec, 2023 - Comments: 0

Thermal analysis is being driven much further left in the design, fueled by demand for increased transistor density and more features on a chip or in a package, as well as the unique ways the various components may be exercised or stressed. However, getting a clear picture of the thermal activity in advanced-node chips and packages is extremely complex, and it can vary significantly by use c... » read more

BYO NPU Benchmarks
By Steve Roddy - 14 Dec, 2023 - Comments: 0

In our last blog post, we highlighted the ways that NPU vendors can shade the truth about performance on benchmark networks such that comparing common performance scores such as “Resnet50 Inferences / Second” can be a futile exercise. But there is a straight-forward, low-investment method for an IP evaluator to short-circuit all the vendor shenanigans and get a solid apples-to-apples result... » read more

Data Formats For Inference On The Edge
By Brian Bailey - 14 Dec, 2023 - Comments: 0

AI/ML training traditionally has been performed using floating point data formats, primarily because that is what was available. But this usually isn't a viable option for inference on the edge, where more compact data formats are needed to reduce area and power. Compact data formats use less space, which is important in edge devices, but the bigger concern is the power needed to move around... » read more

The Journey To Exascale Computing And Beyond
By Steven Woo - 14 Dec, 2023 - Comments: 0

High performance computing witnessed one of its most ambitious leaps forward with the development of the US supercomputer “Frontier.” As Scott Atchley from Oak Ridge National Laboratory discussed at Supercomputing 23 (SC23) in Denver last month, the Frontier had the ambitious goal of achieving performance levels 1000 times higher than the petascale systems that preceded it, while also stayi... » read more

Requirements For The Efficient Implementation Of AI Solutions On Edge Devices
By André Schneider - 14 Dec, 2023 - Comments: 0

By André Schneider, Olaf Enge-Rosenblatt, and Björn Zeugmann In recent years, there has been a growing tendency to implement data-driven approaches for the continuous monitoring of industrial plants as part of digitalization and Industry 4.0 initiatives. The hope is to detect critical conditions at an early stage, minimize maintenance and downtimes, and continuously achieve high product qu... » read more

Next-Gen Power Integrity Challenges
By Ed Sperling - 14 Dec, 2023 - Comments: 0

Experts at the Table: Semiconductor Engineering sat down to discuss power integrity challenges and best practices in designs at 7nm and below, and in 2.5D and 3D-IC packages, with Chip Stratakos, partner, physical design at Microsoft; Mohit Jain, principal engineer at Qualcomm; Thomas Quan, director at TSMC; and Murat Becer, vice president at Ansys. What follows are excerpts of that conversatio... » read more

Advanced Design Debug Demands Integrated Verification Management
By Robert Ruiz - 14 Dec, 2023 - Comments: 0

Design verification has been the dominant portion of chip development for years, and the challenges grow bigger every day. Single dies continue to grow in transistor count and complexity. Advanced techniques such as 2.5D and 3D multi-die systems and emerging technologies such as wafer-scale integration pack even more transistors and functionality into a single device. This situation has created... » read more

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