Will There Be Enough Silicon Wafers?


The silicon wafer industry, a critical part of the IC supply chain, is undergoing a new and perhaps alarming wave of merger and acquisition activity. While consolidation in this sector is not new, the pace of M&A activity is picking up and there are fewer companies left. Silicon wafer makers produce and sell raw silicon wafers to chipmakers, which process them into chips. But despite con... » read more

OLEDs Shine In Phones, TVs, Lights


OLEDs are coming—everywhere. While the new iPhone 7 models do not have organic light-emitting diode (OLED) displays, those handsets are likely to be the last Apple will offer before it makes the smartphone transition to OLED displays next year. The Apple Watch, however, does have a flexible OLED display with a sapphire crystal cover or an Ion-X glass cover, and the Apple Watch Series 2 ... » read more

Will GPU-Acceleration Mean The End Of Empirical Mask Models?


Shrinking mask feature sizes and increasing proximity effects are driving the adoption of simulation-based mask processing. Empirical models have been most widely used to date, because they are faster to simulate. Today, GPU-acceleration is enabling fast simulation using physical models. Does the ability of GPU-acceleration to make physical models a practical solution mean the end of empirical ... » read more

What Happened To Inverse Lithography?


Nearly 10 years ago, the industry rolled out a potentially disruptive technique called inverse lithography technology (ILT). But ILT was ahead of its time, causing the industry to push out the technology and relegate it to niche-oriented applications. Today, though, ILT is getting new attention as the semiconductor industry pushes toward 7nm, and perhaps beyond. ILT is not a next-generation ... » read more

China Ramps Up Power IC Manufacturing


In addition to changes in power devices being implemented to meet market trends that I discussed in previous posts, there are significant shifts taking place in the locations where these components are manufactured. Over the past 10 years, we’ve seen an increase in power device manufacturing in China, Europe and South East Asia and a subsequent drop off in North America. If we look at ... » read more

2.5D Surprises And Alternatives


Semiconductor Engineering sat to discuss advanced packaging issues with Juan Rey, senior director of engineering for Calibre at [getentity id="22017" e_name="Mentor Graphics"]; Max Min, senior technical manager at [getentity id="22865" e_name="Samsung"]; and Lisa Minwell, [getentity id="22242" e_name="eSilicon's"] senior director of IP marketing. What follows are excerpts of that conversation. ... » read more

What To Do With A GaN PDK


Wolfspeed's Jeremy Fisher provides a hands on demo of how his group achieved a first-pass run of a 40GHz MMIC chip using using a PDK for its 0.14 micron process. [youtube vid=i7dsQG8CTO4] » read more

Application Of Overlay Modeling And Control With Zernike Polynomials In An HVM Environment


By JawWuk Ju, MinGyu Kim and JuHan Lee of SK Hynix; Jeremy Nabeth, John C. Robinson and Bill Pierson of KLA-Tencor; and Sanghuck Jeon and Hoyoung Heo of KLA-Tencor Korea. Abstract Shrinking technology nodes and smaller process margins require improved photolithography overlay control. Generally, overlay measurement results are modeled with Cartesian polynomial functions for both intra-field... » read more

Testing the Big Bang of Smart Devices


Thanks to the proliferation of smart devices in the Internet of Things (IoT), it’s a circumstance not unlike the overwhelming sense of wonder and bewilderment that ancient Greek astronomer Ptolemy must have felt when gazing up at a sky full of stars on a clear winter’s night, trying to rationalize the vast tableau before him. But just as we wouldn’t critique early astronomers and philo... » read more

A Novel Approach To Dummy Fill For Analog Designs Using Calibre SmartFill


With small geometry silicon processes, additional nonfunctional geometric structures are required to maintain layer planarity during the chemical/mechanical polishing (CMP) phase of processing. The automated layout flows to generate such geometries tend to be designed primarily for large system on chip (SOC) digital designs. When applied to mixed-signal layouts, these flows have been seen to ha... » read more

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